CMSIS STM32F334x8 Devices Peripheral Access Layer Header File. More...

#include "core_cm4.h"
#include "system_stm32f3xx.h"
#include <stdint.h>

Classes
struct	ADC_TypeDef
	Analog to Digital Converter. More...

struct	ADC_Common_TypeDef

struct	CAN_TxMailBox_TypeDef
	Controller Area Network TxMailBox. More...

struct	CAN_FIFOMailBox_TypeDef
	Controller Area Network FIFOMailBox. More...

struct	CAN_FilterRegister_TypeDef
	Controller Area Network FilterRegister. More...

struct	CAN_TypeDef
	Controller Area Network. More...

struct	COMP_TypeDef
	Analog Comparators. More...

struct	COMP_Common_TypeDef

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DMA_Channel_TypeDef
	DMA Controller. More...

struct	DMA_TypeDef

struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	OB_TypeDef
	Option Bytes Registers. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	OPAMP_TypeDef
	Operational Amplifier (OPAMP) More...

struct	HRTIM_Master_TypeDef
	High resolution Timer (HRTIM) More...

struct	HRTIM_Timerx_TypeDef

struct	HRTIM_Common_TypeDef

struct	HRTIM_TypeDef

struct	SYSCFG_TypeDef
	System configuration controller. More...

struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	TIM_TypeDef
	TIM. More...

struct	TSC_TypeDef
	Touch Sensing Controller (TSC) More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

Macros
#define	__CM4_REV 0x0001U
	Configuration of the Cortex-M4 Processor and Core Peripherals. More...

#define	__MPU_PRESENT 0U

#define	__NVIC_PRIO_BITS 4U

#define	__Vendor_SysTickConfig 0U

#define	__FPU_PRESENT 1U

#define	FLASH_BASE 0x08000000UL

#define	CCMDATARAM_BASE 0x10000000UL

#define	SRAM_BASE 0x20000000UL

#define	PERIPH_BASE 0x40000000UL

#define	SRAM_BB_BASE 0x22000000UL

#define	PERIPH_BB_BASE 0x42000000UL

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)

#define	AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)

#define	RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)

#define	USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)

#define	USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)

#define	CAN_BASE (APB1PERIPH_BASE + 0x00006400UL)

#define	PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)

#define	DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL)

#define	DAC2_BASE (APB1PERIPH_BASE + 0x00009800UL)

#define	DAC_BASE DAC1_BASE

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)

#define	COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL)

#define	COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL)

#define	COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL)

#define	COMP_BASE COMP2_BASE

#define	OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL)

#define	OPAMP_BASE OPAMP2_BASE

#define	EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)

#define	USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)

#define	TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL)

#define	TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)

#define	TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)

#define	HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400UL)

#define	HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)

#define	HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)

#define	HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)

#define	HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)

#define	HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)

#define	HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)

#define	DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)

#define	DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)

#define	DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)

#define	DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)

#define	DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)

#define	DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)

#define	DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL)

#define	OB_BASE 0x1FFFF800UL

#define	FLASHSIZE_BASE 0x1FFFF7CCUL

#define	UID_BASE 0x1FFFF7ACUL

#define	CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)

#define	TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)

#define	GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)

#define	GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)

#define	GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)

#define	GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)

#define	GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)

#define	ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)

#define	ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)

#define	ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)

#define	DBGMCU_BASE 0xE0042000UL

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	CAN ((CAN_TypeDef *) CAN_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC ((DAC_TypeDef *) DAC_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP4 ((COMP_TypeDef *) COMP4_BASE)

#define	COMP6 ((COMP_TypeDef *) COMP6_BASE)

#define	COMP ((COMP_TypeDef *) COMP_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

#define	DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

#define	DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

#define	DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

#define	DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

#define	DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

#define	DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	OB ((OB_TypeDef *) OB_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	TSC ((TSC_TypeDef *) TSC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)

#define	ADC1_2_COMMON ADC12_COMMON

#define	ADC5_V1_1

#define	ADC_MULTIMODE_SUPPORT

#define	ADC_ISR_ADRDY_Pos (0U)

#define	ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

#define	ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

#define	ADC_ISR_EOSMP_Pos (1U)

#define	ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

#define	ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

#define	ADC_ISR_EOC_Pos (2U)

#define	ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

#define	ADC_ISR_EOC ADC_ISR_EOC_Msk

#define	ADC_ISR_EOS_Pos (3U)

#define	ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

#define	ADC_ISR_EOS ADC_ISR_EOS_Msk

#define	ADC_ISR_OVR_Pos (4U)

#define	ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

#define	ADC_ISR_OVR ADC_ISR_OVR_Msk

#define	ADC_ISR_JEOC_Pos (5U)

#define	ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)

#define	ADC_ISR_JEOC ADC_ISR_JEOC_Msk

#define	ADC_ISR_JEOS_Pos (6U)

#define	ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)

#define	ADC_ISR_JEOS ADC_ISR_JEOS_Msk

#define	ADC_ISR_AWD1_Pos (7U)

#define	ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

#define	ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

#define	ADC_ISR_AWD2_Pos (8U)

#define	ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

#define	ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

#define	ADC_ISR_AWD3_Pos (9U)

#define	ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

#define	ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

#define	ADC_ISR_JQOVF_Pos (10U)

#define	ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)

#define	ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk

#define	ADC_ISR_ADRD (ADC_ISR_ADRDY)

#define	ADC_IER_ADRDYIE_Pos (0U)

#define	ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

#define	ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

#define	ADC_IER_EOSMPIE_Pos (1U)

#define	ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

#define	ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

#define	ADC_IER_EOCIE_Pos (2U)

#define	ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

#define	ADC_IER_EOCIE ADC_IER_EOCIE_Msk

#define	ADC_IER_EOSIE_Pos (3U)

#define	ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

#define	ADC_IER_EOSIE ADC_IER_EOSIE_Msk

#define	ADC_IER_OVRIE_Pos (4U)

#define	ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

#define	ADC_IER_OVRIE ADC_IER_OVRIE_Msk

#define	ADC_IER_JEOCIE_Pos (5U)

#define	ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)

#define	ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk

#define	ADC_IER_JEOSIE_Pos (6U)

#define	ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)

#define	ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk

#define	ADC_IER_AWD1IE_Pos (7U)

#define	ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

#define	ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

#define	ADC_IER_AWD2IE_Pos (8U)

#define	ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

#define	ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

#define	ADC_IER_AWD3IE_Pos (9U)

#define	ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

#define	ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

#define	ADC_IER_JQOVFIE_Pos (10U)

#define	ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)

#define	ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk

#define	ADC_IER_RDY (ADC_IER_ADRDYIE)

#define	ADC_IER_EOSMP (ADC_IER_EOSMPIE)

#define	ADC_IER_EOC (ADC_IER_EOCIE)

#define	ADC_IER_EOS (ADC_IER_EOSIE)

#define	ADC_IER_OVR (ADC_IER_OVRIE)

#define	ADC_IER_JEOC (ADC_IER_JEOCIE)

#define	ADC_IER_JEOS (ADC_IER_JEOSIE)

#define	ADC_IER_AWD1 (ADC_IER_AWD1IE)

#define	ADC_IER_AWD2 (ADC_IER_AWD2IE)

#define	ADC_IER_AWD3 (ADC_IER_AWD3IE)

#define	ADC_IER_JQOVF (ADC_IER_JQOVFIE)

#define	ADC_CR_ADEN_Pos (0U)

#define	ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

#define	ADC_CR_ADEN ADC_CR_ADEN_Msk

#define	ADC_CR_ADDIS_Pos (1U)

#define	ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

#define	ADC_CR_ADDIS ADC_CR_ADDIS_Msk

#define	ADC_CR_ADSTART_Pos (2U)

#define	ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

#define	ADC_CR_ADSTART ADC_CR_ADSTART_Msk

#define	ADC_CR_JADSTART_Pos (3U)

#define	ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)

#define	ADC_CR_JADSTART ADC_CR_JADSTART_Msk

#define	ADC_CR_ADSTP_Pos (4U)

#define	ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

#define	ADC_CR_ADSTP ADC_CR_ADSTP_Msk

#define	ADC_CR_JADSTP_Pos (5U)

#define	ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)

#define	ADC_CR_JADSTP ADC_CR_JADSTP_Msk

#define	ADC_CR_ADVREGEN_Pos (28U)

#define	ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

#define	ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADCALDIF_Pos (30U)

#define	ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)

#define	ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk

#define	ADC_CR_ADCAL_Pos (31U)

#define	ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

#define	ADC_CR_ADCAL ADC_CR_ADCAL_Msk

#define	ADC_CFGR_DMAEN_Pos (0U)

#define	ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)

#define	ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk

#define	ADC_CFGR_DMACFG_Pos (1U)

#define	ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)

#define	ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk

#define	ADC_CFGR_RES_Pos (3U)

#define	ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES ADC_CFGR_RES_Msk

#define	ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_ALIGN_Pos (5U)

#define	ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)

#define	ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk

#define	ADC_CFGR_EXTSEL_Pos (6U)

#define	ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk

#define	ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTEN_Pos (10U)

#define	ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk

#define	ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_OVRMOD_Pos (12U)

#define	ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)

#define	ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk

#define	ADC_CFGR_CONT_Pos (13U)

#define	ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)

#define	ADC_CFGR_CONT ADC_CFGR_CONT_Msk

#define	ADC_CFGR_AUTDLY_Pos (14U)

#define	ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)

#define	ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk

#define	ADC_CFGR_DISCEN_Pos (16U)

#define	ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)

#define	ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk

#define	ADC_CFGR_DISCNUM_Pos (17U)

#define	ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk

#define	ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_JDISCEN_Pos (20U)

#define	ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)

#define	ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk

#define	ADC_CFGR_JQM_Pos (21U)

#define	ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)

#define	ADC_CFGR_JQM ADC_CFGR_JQM_Msk

#define	ADC_CFGR_AWD1SGL_Pos (22U)

#define	ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)

#define	ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk

#define	ADC_CFGR_AWD1EN_Pos (23U)

#define	ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)

#define	ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk

#define	ADC_CFGR_JAWD1EN_Pos (24U)

#define	ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)

#define	ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk

#define	ADC_CFGR_JAUTO_Pos (25U)

#define	ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)

#define	ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk

#define	ADC_CFGR_AWD1CH_Pos (26U)

#define	ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk

#define	ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AUTOFF_Pos (15U)

#define	ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos)

#define	ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk

#define	ADC_SMPR1_SMP0_Pos (0U)

#define	ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk

#define	ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP1_Pos (3U)

#define	ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk

#define	ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP2_Pos (6U)

#define	ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk

#define	ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP3_Pos (9U)

#define	ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk

#define	ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP4_Pos (12U)

#define	ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk

#define	ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP5_Pos (15U)

#define	ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk

#define	ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP6_Pos (18U)

#define	ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk

#define	ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP7_Pos (21U)

#define	ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk

#define	ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP8_Pos (24U)

#define	ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk

#define	ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP9_Pos (27U)

#define	ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk

#define	ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR2_SMP10_Pos (0U)

#define	ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk

#define	ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP11_Pos (3U)

#define	ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk

#define	ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP12_Pos (6U)

#define	ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk

#define	ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP13_Pos (9U)

#define	ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk

#define	ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP14_Pos (12U)

#define	ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk

#define	ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP15_Pos (15U)

#define	ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk

#define	ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP16_Pos (18U)

#define	ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk

#define	ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP17_Pos (21U)

#define	ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk

#define	ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP18_Pos (24U)

#define	ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk

#define	ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_TR1_LT1_Pos (0U)

#define	ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1 ADC_TR1_LT1_Msk

#define	ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_HT1_Pos (16U)

#define	ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1 ADC_TR1_HT1_Msk

#define	ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)

#define	ADC_TR2_LT2_Pos (0U)

#define	ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2 ADC_TR2_LT2_Msk

#define	ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_HT2_Pos (16U)

#define	ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2 ADC_TR2_HT2_Msk

#define	ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)

#define	ADC_TR3_LT3_Pos (0U)

#define	ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3 ADC_TR3_LT3_Msk

#define	ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_HT3_Pos (16U)

#define	ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3 ADC_TR3_HT3_Msk

#define	ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)

#define	ADC_SQR1_L_Pos (0U)

#define	ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L ADC_SQR1_L_Msk

#define	ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_SQ1_Pos (6U)

#define	ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk

#define	ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ2_Pos (12U)

#define	ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk

#define	ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ3_Pos (18U)

#define	ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk

#define	ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ4_Pos (24U)

#define	ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk

#define	ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR2_SQ5_Pos (0U)

#define	ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk

#define	ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ6_Pos (6U)

#define	ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk

#define	ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ7_Pos (12U)

#define	ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

#define	ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ8_Pos (18U)

#define	ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

#define	ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ9_Pos (24U)

#define	ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

#define	ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR3_SQ10_Pos (0U)

#define	ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk

#define	ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ11_Pos (6U)

#define	ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk

#define	ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ12_Pos (12U)

#define	ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk

#define	ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ13_Pos (18U)

#define	ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk

#define	ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ14_Pos (24U)

#define	ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk

#define	ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR4_SQ15_Pos (0U)

#define	ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk

#define	ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ16_Pos (6U)

#define	ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk

#define	ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)

#define	ADC_DR_RDATA_Pos (0U)

#define	ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA ADC_DR_RDATA_Msk

#define	ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)

#define	ADC_JSQR_JL_Pos (0U)

#define	ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL ADC_JSQR_JL_Msk

#define	ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JEXTSEL_Pos (2U)

#define	ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk

#define	ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTEN_Pos (6U)

#define	ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk

#define	ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JSQ1_Pos (8U)

#define	ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

#define	ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ2_Pos (14U)

#define	ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

#define	ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ3_Pos (20U)

#define	ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

#define	ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ4_Pos (26U)

#define	ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

#define	ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_OFR1_OFFSET1_Pos (0U)

#define	ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk

#define	ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_CH_Pos (26U)

#define	ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk

#define	ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_EN_Pos (31U)

#define	ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)

#define	ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk

#define	ADC_OFR2_OFFSET2_Pos (0U)

#define	ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk

#define	ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_CH_Pos (26U)

#define	ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk

#define	ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_EN_Pos (31U)

#define	ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)

#define	ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk

#define	ADC_OFR3_OFFSET3_Pos (0U)

#define	ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk

#define	ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_CH_Pos (26U)

#define	ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk

#define	ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_EN_Pos (31U)

#define	ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)

#define	ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk

#define	ADC_OFR4_OFFSET4_Pos (0U)

#define	ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk

#define	ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_CH_Pos (26U)

#define	ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk

#define	ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_EN_Pos (31U)

#define	ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)

#define	ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk

#define	ADC_JDR1_JDATA_Pos (0U)

#define	ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

#define	ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR2_JDATA_Pos (0U)

#define	ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

#define	ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR3_JDATA_Pos (0U)

#define	ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

#define	ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR4_JDATA_Pos (0U)

#define	ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

#define	ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_AWD2CR_AWD2CH_Pos (1U)

#define	ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

#define	ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD3CR_AWD3CH_Pos (1U)

#define	ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

#define	ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_DIFSEL_DIFSEL_Pos (1U)

#define	ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk

#define	ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_CALFACT_CALFACT_S_Pos (0U)

#define	ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk

#define	ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_D_Pos (16U)

#define	ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk

#define	ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC12_CSR_ADRDY_MST_Pos (0U)

#define	ADC12_CSR_ADRDY_MST_Msk (0x1UL << ADC12_CSR_ADRDY_MST_Pos)

#define	ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk

#define	ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)

#define	ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos)

#define	ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk

#define	ADC12_CSR_ADRDY_EOC_MST_Pos (2U)

#define	ADC12_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos)

#define	ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk

#define	ADC12_CSR_ADRDY_EOS_MST_Pos (3U)

#define	ADC12_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos)

#define	ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk

#define	ADC12_CSR_ADRDY_OVR_MST_Pos (4U)

#define	ADC12_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos)

#define	ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk

#define	ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)

#define	ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos)

#define	ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk

#define	ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)

#define	ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos)

#define	ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk

#define	ADC12_CSR_AWD1_MST_Pos (7U)

#define	ADC12_CSR_AWD1_MST_Msk (0x1UL << ADC12_CSR_AWD1_MST_Pos)

#define	ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk

#define	ADC12_CSR_AWD2_MST_Pos (8U)

#define	ADC12_CSR_AWD2_MST_Msk (0x1UL << ADC12_CSR_AWD2_MST_Pos)

#define	ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk

#define	ADC12_CSR_AWD3_MST_Pos (9U)

#define	ADC12_CSR_AWD3_MST_Msk (0x1UL << ADC12_CSR_AWD3_MST_Pos)

#define	ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk

#define	ADC12_CSR_JQOVF_MST_Pos (10U)

#define	ADC12_CSR_JQOVF_MST_Msk (0x1UL << ADC12_CSR_JQOVF_MST_Pos)

#define	ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk

#define	ADC12_CSR_ADRDY_SLV_Pos (16U)

#define	ADC12_CSR_ADRDY_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)

#define	ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk

#define	ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)

#define	ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk

#define	ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)

#define	ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk

#define	ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)

#define	ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk

#define	ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

#define	ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

#define	ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

#define	ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)

#define	ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos)

#define	ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk

#define	ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)

#define	ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos)

#define	ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk

#define	ADC12_CSR_AWD1_SLV_Pos (23U)

#define	ADC12_CSR_AWD1_SLV_Msk (0x1UL << ADC12_CSR_AWD1_SLV_Pos)

#define	ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk

#define	ADC12_CSR_AWD2_SLV_Pos (24U)

#define	ADC12_CSR_AWD2_SLV_Msk (0x1UL << ADC12_CSR_AWD2_SLV_Pos)

#define	ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk

#define	ADC12_CSR_AWD3_SLV_Pos (25U)

#define	ADC12_CSR_AWD3_SLV_Msk (0x1UL << ADC12_CSR_AWD3_SLV_Pos)

#define	ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk

#define	ADC12_CSR_JQOVF_SLV_Pos (26U)

#define	ADC12_CSR_JQOVF_SLV_Msk (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)

#define	ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk

#define	ADC34_CSR_ADRDY_MST_Pos (0U)

#define	ADC34_CSR_ADRDY_MST_Msk (0x1UL << ADC34_CSR_ADRDY_MST_Pos)

#define	ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk

#define	ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)

#define	ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos)

#define	ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk

#define	ADC34_CSR_ADRDY_EOC_MST_Pos (2U)

#define	ADC34_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos)

#define	ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk

#define	ADC34_CSR_ADRDY_EOS_MST_Pos (3U)

#define	ADC34_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos)

#define	ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk

#define	ADC34_CSR_ADRDY_OVR_MST_Pos (4U)

#define	ADC34_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos)

#define	ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk

#define	ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)

#define	ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos)

#define	ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk

#define	ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)

#define	ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos)

#define	ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk

#define	ADC34_CSR_AWD1_MST_Pos (7U)

#define	ADC34_CSR_AWD1_MST_Msk (0x1UL << ADC34_CSR_AWD1_MST_Pos)

#define	ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk

#define	ADC34_CSR_AWD2_MST_Pos (8U)

#define	ADC34_CSR_AWD2_MST_Msk (0x1UL << ADC34_CSR_AWD2_MST_Pos)

#define	ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk

#define	ADC34_CSR_AWD3_MST_Pos (9U)

#define	ADC34_CSR_AWD3_MST_Msk (0x1UL << ADC34_CSR_AWD3_MST_Pos)

#define	ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk

#define	ADC34_CSR_JQOVF_MST_Pos (10U)

#define	ADC34_CSR_JQOVF_MST_Msk (0x1UL << ADC34_CSR_JQOVF_MST_Pos)

#define	ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk

#define	ADC34_CSR_ADRDY_SLV_Pos (16U)

#define	ADC34_CSR_ADRDY_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)

#define	ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk

#define	ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)

#define	ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk

#define	ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)

#define	ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk

#define	ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)

#define	ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk

#define	ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

#define	ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

#define	ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

#define	ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)

#define	ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos)

#define	ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk

#define	ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)

#define	ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos)

#define	ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk

#define	ADC34_CSR_AWD1_SLV_Pos (23U)

#define	ADC34_CSR_AWD1_SLV_Msk (0x1UL << ADC34_CSR_AWD1_SLV_Pos)

#define	ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk

#define	ADC34_CSR_AWD2_SLV_Pos (24U)

#define	ADC34_CSR_AWD2_SLV_Msk (0x1UL << ADC34_CSR_AWD2_SLV_Pos)

#define	ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk

#define	ADC34_CSR_AWD3_SLV_Pos (25U)

#define	ADC34_CSR_AWD3_SLV_Msk (0x1UL << ADC34_CSR_AWD3_SLV_Pos)

#define	ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk

#define	ADC34_CSR_JQOVF_SLV_Pos (26U)

#define	ADC34_CSR_JQOVF_SLV_Msk (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)

#define	ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk

#define	ADC12_CCR_MULTI_Pos (0U)

#define	ADC12_CCR_MULTI_Msk (0x1FUL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk

#define	ADC12_CCR_MULTI_0 (0x01UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_1 (0x02UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_2 (0x04UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_3 (0x08UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_4 (0x10UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_DELAY_Pos (8U)

#define	ADC12_CCR_DELAY_Msk (0xFUL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk

#define	ADC12_CCR_DELAY_0 (0x1UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_1 (0x2UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_2 (0x4UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_3 (0x8UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DMACFG_Pos (13U)

#define	ADC12_CCR_DMACFG_Msk (0x1UL << ADC12_CCR_DMACFG_Pos)

#define	ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk

#define	ADC12_CCR_MDMA_Pos (14U)

#define	ADC12_CCR_MDMA_Msk (0x3UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk

#define	ADC12_CCR_MDMA_0 (0x1UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_MDMA_1 (0x2UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_CKMODE_Pos (16U)

#define	ADC12_CCR_CKMODE_Msk (0x3UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk

#define	ADC12_CCR_CKMODE_0 (0x1UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_CKMODE_1 (0x2UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_VREFEN_Pos (22U)

#define	ADC12_CCR_VREFEN_Msk (0x1UL << ADC12_CCR_VREFEN_Pos)

#define	ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk

#define	ADC12_CCR_TSEN_Pos (23U)

#define	ADC12_CCR_TSEN_Msk (0x1UL << ADC12_CCR_TSEN_Pos)

#define	ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk

#define	ADC12_CCR_VBATEN_Pos (24U)

#define	ADC12_CCR_VBATEN_Msk (0x1UL << ADC12_CCR_VBATEN_Pos)

#define	ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk

#define	ADC12_CDR_RDATA_MST_Pos (0U)

#define	ADC12_CDR_RDATA_MST_Msk (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk

#define	ADC12_CDR_RDATA_MST_0 (0x0001UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_1 (0x0002UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_2 (0x0004UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_3 (0x0008UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_4 (0x0010UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_5 (0x0020UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_6 (0x0040UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_7 (0x0080UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_8 (0x0100UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_9 (0x0200UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_10 (0x0400UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_11 (0x0800UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_12 (0x1000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_13 (0x2000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_14 (0x4000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_15 (0x8000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_SLV_Pos (16U)

#define	ADC12_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk

#define	ADC12_CDR_RDATA_SLV_0 (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_1 (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_2 (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_3 (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_4 (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_5 (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_6 (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_7 (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_8 (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_9 (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_10 (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_11 (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_12 (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_13 (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_14 (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_15 (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC_CSR_ADRDY_MST_Pos (0U)

#define	ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)

#define	ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk

#define	ADC_CSR_EOSMP_MST_Pos (1U)

#define	ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)

#define	ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk

#define	ADC_CSR_EOC_MST_Pos (2U)

#define	ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)

#define	ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk

#define	ADC_CSR_EOS_MST_Pos (3U)

#define	ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)

#define	ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk

#define	ADC_CSR_OVR_MST_Pos (4U)

#define	ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)

#define	ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk

#define	ADC_CSR_JEOC_MST_Pos (5U)

#define	ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)

#define	ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk

#define	ADC_CSR_JEOS_MST_Pos (6U)

#define	ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)

#define	ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk

#define	ADC_CSR_AWD1_MST_Pos (7U)

#define	ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)

#define	ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk

#define	ADC_CSR_AWD2_MST_Pos (8U)

#define	ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)

#define	ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk

#define	ADC_CSR_AWD3_MST_Pos (9U)

#define	ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)

#define	ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk

#define	ADC_CSR_JQOVF_MST_Pos (10U)

#define	ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)

#define	ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk

#define	ADC_CSR_ADRDY_SLV_Pos (16U)

#define	ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)

#define	ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk

#define	ADC_CSR_EOSMP_SLV_Pos (17U)

#define	ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)

#define	ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk

#define	ADC_CSR_EOC_SLV_Pos (18U)

#define	ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)

#define	ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk

#define	ADC_CSR_EOS_SLV_Pos (19U)

#define	ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)

#define	ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk

#define	ADC_CSR_OVR_SLV_Pos (20U)

#define	ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)

#define	ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk

#define	ADC_CSR_JEOC_SLV_Pos (21U)

#define	ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)

#define	ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk

#define	ADC_CSR_JEOS_SLV_Pos (22U)

#define	ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)

#define	ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk

#define	ADC_CSR_AWD1_SLV_Pos (23U)

#define	ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)

#define	ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk

#define	ADC_CSR_AWD2_SLV_Pos (24U)

#define	ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)

#define	ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk

#define	ADC_CSR_AWD3_SLV_Pos (25U)

#define	ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)

#define	ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk

#define	ADC_CSR_JQOVF_SLV_Pos (26U)

#define	ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)

#define	ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk

#define	ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST

#define	ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST

#define	ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST

#define	ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST

#define	ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST

#define	ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST

#define	ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV

#define	ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV

#define	ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV

#define	ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV

#define	ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV

#define	ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV

#define	ADC_CCR_DUAL_Pos (0U)

#define	ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL ADC_CCR_DUAL_Msk

#define	ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DELAY_Pos (8U)

#define	ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY ADC_CCR_DELAY_Msk

#define	ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DMACFG_Pos (13U)

#define	ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)

#define	ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk

#define	ADC_CCR_MDMA_Pos (14U)

#define	ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA ADC_CCR_MDMA_Msk

#define	ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_CKMODE_Pos (16U)

#define	ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk

#define	ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_VREFEN_Pos (22U)

#define	ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

#define	ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

#define	ADC_CCR_TSEN_Pos (23U)

#define	ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

#define	ADC_CCR_TSEN ADC_CCR_TSEN_Msk

#define	ADC_CCR_VBATEN_Pos (24U)

#define	ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

#define	ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

#define	ADC_CCR_MULTI (ADC_CCR_DUAL)

#define	ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)

#define	ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)

#define	ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)

#define	ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)

#define	ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)

#define	ADC_CDR_RDATA_MST_Pos (0U)

#define	ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk

#define	ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_SLV_Pos (16U)

#define	ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk

#define	ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)

#define	COMP_V1_3_0_0

#define	COMP2_CSR_COMP2EN_Pos (0U)

#define	COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos)

#define	COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk

#define	COMP2_CSR_COMP2INSEL_Pos (4U)

#define	COMP2_CSR_COMP2INSEL_Msk (0x40007UL << COMP2_CSR_COMP2INSEL_Pos)

#define	COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk

#define	COMP2_CSR_COMP2INSEL_0 (0x00000010U)

#define	COMP2_CSR_COMP2INSEL_1 (0x00000020U)

#define	COMP2_CSR_COMP2INSEL_2 (0x00000040U)

#define	COMP2_CSR_COMP2INSEL_3 (0x00400000U)

#define	COMP2_CSR_COMP2OUTSEL_Pos (10U)

#define	COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk

#define	COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2POL_Pos (15U)

#define	COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos)

#define	COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk

#define	COMP2_CSR_COMP2BLANKING_Pos (18U)

#define	COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk

#define	COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2OUT_Pos (30U)

#define	COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos)

#define	COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk

#define	COMP2_CSR_COMP2LOCK_Pos (31U)

#define	COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos)

#define	COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk

#define	COMP4_CSR_COMP4EN_Pos (0U)

#define	COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos)

#define	COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk

#define	COMP4_CSR_COMP4INSEL_Pos (4U)

#define	COMP4_CSR_COMP4INSEL_Msk (0x40007UL << COMP4_CSR_COMP4INSEL_Pos)

#define	COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk

#define	COMP4_CSR_COMP4INSEL_0 (0x00000010U)

#define	COMP4_CSR_COMP4INSEL_1 (0x00000020U)

#define	COMP4_CSR_COMP4INSEL_2 (0x00000040U)

#define	COMP4_CSR_COMP4INSEL_3 (0x00400000U)

#define	COMP4_CSR_COMP4OUTSEL_Pos (10U)

#define	COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk

#define	COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4POL_Pos (15U)

#define	COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos)

#define	COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk

#define	COMP4_CSR_COMP4BLANKING_Pos (18U)

#define	COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk

#define	COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4OUT_Pos (30U)

#define	COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos)

#define	COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk

#define	COMP4_CSR_COMP4LOCK_Pos (31U)

#define	COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos)

#define	COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk

#define	COMP6_CSR_COMP6EN_Pos (0U)

#define	COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos)

#define	COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk

#define	COMP6_CSR_COMP6INSEL_Pos (4U)

#define	COMP6_CSR_COMP6INSEL_Msk (0x40007UL << COMP6_CSR_COMP6INSEL_Pos)

#define	COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk

#define	COMP6_CSR_COMP6INSEL_0 (0x00000010U)

#define	COMP6_CSR_COMP6INSEL_1 (0x00000020U)

#define	COMP6_CSR_COMP6INSEL_2 (0x00000040U)

#define	COMP6_CSR_COMP6INSEL_3 (0x00400000U)

#define	COMP6_CSR_COMP6OUTSEL_Pos (10U)

#define	COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk

#define	COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6POL_Pos (15U)

#define	COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos)

#define	COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk

#define	COMP6_CSR_COMP6BLANKING_Pos (18U)

#define	COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk

#define	COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6OUT_Pos (30U)

#define	COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos)

#define	COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk

#define	COMP6_CSR_COMP6LOCK_Pos (31U)

#define	COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos)

#define	COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk

#define	COMP_CSR_COMPxEN_Pos (0U)

#define	COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)

#define	COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk

#define	COMP_CSR_COMPxINSEL_Pos (4U)

#define	COMP_CSR_COMPxINSEL_Msk (0x40007UL << COMP_CSR_COMPxINSEL_Pos)

#define	COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk

#define	COMP_CSR_COMPxINSEL_0 (0x00000010U)

#define	COMP_CSR_COMPxINSEL_1 (0x00000020U)

#define	COMP_CSR_COMPxINSEL_2 (0x00000040U)

#define	COMP_CSR_COMPxINSEL_3 (0x00400000U)

#define	COMP_CSR_COMPxOUTSEL_Pos (10U)

#define	COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk

#define	COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxPOL_Pos (15U)

#define	COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos)

#define	COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk

#define	COMP_CSR_COMPxBLANKING_Pos (18U)

#define	COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk

#define	COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxOUT_Pos (30U)

#define	COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos)

#define	COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk

#define	COMP_CSR_COMPxLOCK_Pos (31U)

#define	COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)

#define	COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk

#define	OPAMP2_CSR_OPAMP2EN_Pos (0U)

#define	OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)

#define	OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk

#define	OPAMP2_CSR_FORCEVP_Pos (1U)

#define	OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)

#define	OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk

#define	OPAMP2_CSR_VPSEL_Pos (2U)

#define	OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk

#define	OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VMSEL_Pos (5U)

#define	OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk

#define	OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_TCMEN_Pos (7U)

#define	OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos)

#define	OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk

#define	OPAMP2_CSR_VMSSEL_Pos (8U)

#define	OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos)

#define	OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk

#define	OPAMP2_CSR_VPSSEL_Pos (9U)

#define	OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk

#define	OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_CALON_Pos (11U)

#define	OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)

#define	OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk

#define	OPAMP2_CSR_CALSEL_Pos (12U)

#define	OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk

#define	OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_PGGAIN_Pos (14U)

#define	OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk

#define	OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_USERTRIM_Pos (18U)

#define	OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)

#define	OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk

#define	OPAMP2_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)

#define	OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk

#define	OPAMP2_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)

#define	OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk

#define	OPAMP2_CSR_TSTREF_Pos (29U)

#define	OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)

#define	OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk

#define	OPAMP2_CSR_OUTCAL_Pos (30U)

#define	OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos)

#define	OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk

#define	OPAMP2_CSR_LOCK_Pos (31U)

#define	OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos)

#define	OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk

#define	OPAMP_CSR_OPAMPxEN_Pos (0U)

#define	OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)

#define	OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk

#define	OPAMP_CSR_FORCEVP_Pos (1U)

#define	OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)

#define	OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk

#define	OPAMP_CSR_VPSEL_Pos (2U)

#define	OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk

#define	OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VMSEL_Pos (5U)

#define	OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk

#define	OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_TCMEN_Pos (7U)

#define	OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos)

#define	OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk

#define	OPAMP_CSR_VMSSEL_Pos (8U)

#define	OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos)

#define	OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk

#define	OPAMP_CSR_VPSSEL_Pos (9U)

#define	OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk

#define	OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_CALON_Pos (11U)

#define	OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)

#define	OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk

#define	OPAMP_CSR_CALSEL_Pos (12U)

#define	OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk

#define	OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_PGGAIN_Pos (14U)

#define	OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk

#define	OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_USERTRIM_Pos (18U)

#define	OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)

#define	OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk

#define	OPAMP_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)

#define	OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk

#define	OPAMP_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)

#define	OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk

#define	OPAMP_CSR_TSTREF_Pos (29U)

#define	OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)

#define	OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk

#define	OPAMP_CSR_OUTCAL_Pos (30U)

#define	OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)

#define	OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk

#define	OPAMP_CSR_LOCK_Pos (31U)

#define	OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)

#define	OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk

#define	CAN_MCR_INRQ_Pos (0U)

#define	CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)

#define	CAN_MCR_INRQ CAN_MCR_INRQ_Msk

#define	CAN_MCR_SLEEP_Pos (1U)

#define	CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)

#define	CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk

#define	CAN_MCR_TXFP_Pos (2U)

#define	CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)

#define	CAN_MCR_TXFP CAN_MCR_TXFP_Msk

#define	CAN_MCR_RFLM_Pos (3U)

#define	CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)

#define	CAN_MCR_RFLM CAN_MCR_RFLM_Msk

#define	CAN_MCR_NART_Pos (4U)

#define	CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)

#define	CAN_MCR_NART CAN_MCR_NART_Msk

#define	CAN_MCR_AWUM_Pos (5U)

#define	CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)

#define	CAN_MCR_AWUM CAN_MCR_AWUM_Msk

#define	CAN_MCR_ABOM_Pos (6U)

#define	CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)

#define	CAN_MCR_ABOM CAN_MCR_ABOM_Msk

#define	CAN_MCR_TTCM_Pos (7U)

#define	CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)

#define	CAN_MCR_TTCM CAN_MCR_TTCM_Msk

#define	CAN_MCR_RESET_Pos (15U)

#define	CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)

#define	CAN_MCR_RESET CAN_MCR_RESET_Msk

#define	CAN_MSR_INAK_Pos (0U)

#define	CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)

#define	CAN_MSR_INAK CAN_MSR_INAK_Msk

#define	CAN_MSR_SLAK_Pos (1U)

#define	CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)

#define	CAN_MSR_SLAK CAN_MSR_SLAK_Msk

#define	CAN_MSR_ERRI_Pos (2U)

#define	CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)

#define	CAN_MSR_ERRI CAN_MSR_ERRI_Msk

#define	CAN_MSR_WKUI_Pos (3U)

#define	CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)

#define	CAN_MSR_WKUI CAN_MSR_WKUI_Msk

#define	CAN_MSR_SLAKI_Pos (4U)

#define	CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)

#define	CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk

#define	CAN_MSR_TXM_Pos (8U)

#define	CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)

#define	CAN_MSR_TXM CAN_MSR_TXM_Msk

#define	CAN_MSR_RXM_Pos (9U)

#define	CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)

#define	CAN_MSR_RXM CAN_MSR_RXM_Msk

#define	CAN_MSR_SAMP_Pos (10U)

#define	CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)

#define	CAN_MSR_SAMP CAN_MSR_SAMP_Msk

#define	CAN_MSR_RX_Pos (11U)

#define	CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)

#define	CAN_MSR_RX CAN_MSR_RX_Msk

#define	CAN_TSR_RQCP0_Pos (0U)

#define	CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)

#define	CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk

#define	CAN_TSR_TXOK0_Pos (1U)

#define	CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)

#define	CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk

#define	CAN_TSR_ALST0_Pos (2U)

#define	CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)

#define	CAN_TSR_ALST0 CAN_TSR_ALST0_Msk

#define	CAN_TSR_TERR0_Pos (3U)

#define	CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)

#define	CAN_TSR_TERR0 CAN_TSR_TERR0_Msk

#define	CAN_TSR_ABRQ0_Pos (7U)

#define	CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)

#define	CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk

#define	CAN_TSR_RQCP1_Pos (8U)

#define	CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)

#define	CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk

#define	CAN_TSR_TXOK1_Pos (9U)

#define	CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)

#define	CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk

#define	CAN_TSR_ALST1_Pos (10U)

#define	CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)

#define	CAN_TSR_ALST1 CAN_TSR_ALST1_Msk

#define	CAN_TSR_TERR1_Pos (11U)

#define	CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)

#define	CAN_TSR_TERR1 CAN_TSR_TERR1_Msk

#define	CAN_TSR_ABRQ1_Pos (15U)

#define	CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)

#define	CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk

#define	CAN_TSR_RQCP2_Pos (16U)

#define	CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)

#define	CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk

#define	CAN_TSR_TXOK2_Pos (17U)

#define	CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)

#define	CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk

#define	CAN_TSR_ALST2_Pos (18U)

#define	CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)

#define	CAN_TSR_ALST2 CAN_TSR_ALST2_Msk

#define	CAN_TSR_TERR2_Pos (19U)

#define	CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)

#define	CAN_TSR_TERR2 CAN_TSR_TERR2_Msk

#define	CAN_TSR_ABRQ2_Pos (23U)

#define	CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)

#define	CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk

#define	CAN_TSR_CODE_Pos (24U)

#define	CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)

#define	CAN_TSR_CODE CAN_TSR_CODE_Msk

#define	CAN_TSR_TME_Pos (26U)

#define	CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)

#define	CAN_TSR_TME CAN_TSR_TME_Msk

#define	CAN_TSR_TME0_Pos (26U)

#define	CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)

#define	CAN_TSR_TME0 CAN_TSR_TME0_Msk

#define	CAN_TSR_TME1_Pos (27U)

#define	CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)

#define	CAN_TSR_TME1 CAN_TSR_TME1_Msk

#define	CAN_TSR_TME2_Pos (28U)

#define	CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)

#define	CAN_TSR_TME2 CAN_TSR_TME2_Msk

#define	CAN_TSR_LOW_Pos (29U)

#define	CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)

#define	CAN_TSR_LOW CAN_TSR_LOW_Msk

#define	CAN_TSR_LOW0_Pos (29U)

#define	CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)

#define	CAN_TSR_LOW0 CAN_TSR_LOW0_Msk

#define	CAN_TSR_LOW1_Pos (30U)

#define	CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)

#define	CAN_TSR_LOW1 CAN_TSR_LOW1_Msk

#define	CAN_TSR_LOW2_Pos (31U)

#define	CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)

#define	CAN_TSR_LOW2 CAN_TSR_LOW2_Msk

#define	CAN_RF0R_FMP0_Pos (0U)

#define	CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)

#define	CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk

#define	CAN_RF0R_FULL0_Pos (3U)

#define	CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)

#define	CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk

#define	CAN_RF0R_FOVR0_Pos (4U)

#define	CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)

#define	CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk

#define	CAN_RF0R_RFOM0_Pos (5U)

#define	CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)

#define	CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk

#define	CAN_RF1R_FMP1_Pos (0U)

#define	CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)

#define	CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk

#define	CAN_RF1R_FULL1_Pos (3U)

#define	CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)

#define	CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk

#define	CAN_RF1R_FOVR1_Pos (4U)

#define	CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)

#define	CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk

#define	CAN_RF1R_RFOM1_Pos (5U)

#define	CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)

#define	CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk

#define	CAN_IER_TMEIE_Pos (0U)

#define	CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)

#define	CAN_IER_TMEIE CAN_IER_TMEIE_Msk

#define	CAN_IER_FMPIE0_Pos (1U)

#define	CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)

#define	CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk

#define	CAN_IER_FFIE0_Pos (2U)

#define	CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)

#define	CAN_IER_FFIE0 CAN_IER_FFIE0_Msk

#define	CAN_IER_FOVIE0_Pos (3U)

#define	CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)

#define	CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk

#define	CAN_IER_FMPIE1_Pos (4U)

#define	CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)

#define	CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk

#define	CAN_IER_FFIE1_Pos (5U)

#define	CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)

#define	CAN_IER_FFIE1 CAN_IER_FFIE1_Msk

#define	CAN_IER_FOVIE1_Pos (6U)

#define	CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)

#define	CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk

#define	CAN_IER_EWGIE_Pos (8U)

#define	CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)

#define	CAN_IER_EWGIE CAN_IER_EWGIE_Msk

#define	CAN_IER_EPVIE_Pos (9U)

#define	CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)

#define	CAN_IER_EPVIE CAN_IER_EPVIE_Msk

#define	CAN_IER_BOFIE_Pos (10U)

#define	CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)

#define	CAN_IER_BOFIE CAN_IER_BOFIE_Msk

#define	CAN_IER_LECIE_Pos (11U)

#define	CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)

#define	CAN_IER_LECIE CAN_IER_LECIE_Msk

#define	CAN_IER_ERRIE_Pos (15U)

#define	CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)

#define	CAN_IER_ERRIE CAN_IER_ERRIE_Msk

#define	CAN_IER_WKUIE_Pos (16U)

#define	CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)

#define	CAN_IER_WKUIE CAN_IER_WKUIE_Msk

#define	CAN_IER_SLKIE_Pos (17U)

#define	CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)

#define	CAN_IER_SLKIE CAN_IER_SLKIE_Msk

#define	CAN_ESR_EWGF_Pos (0U)

#define	CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)

#define	CAN_ESR_EWGF CAN_ESR_EWGF_Msk

#define	CAN_ESR_EPVF_Pos (1U)

#define	CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)

#define	CAN_ESR_EPVF CAN_ESR_EPVF_Msk

#define	CAN_ESR_BOFF_Pos (2U)

#define	CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)

#define	CAN_ESR_BOFF CAN_ESR_BOFF_Msk

#define	CAN_ESR_LEC_Pos (4U)

#define	CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC CAN_ESR_LEC_Msk

#define	CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_TEC_Pos (16U)

#define	CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)

#define	CAN_ESR_TEC CAN_ESR_TEC_Msk

#define	CAN_ESR_REC_Pos (24U)

#define	CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)

#define	CAN_ESR_REC CAN_ESR_REC_Msk

#define	CAN_BTR_BRP_Pos (0U)

#define	CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)

#define	CAN_BTR_BRP CAN_BTR_BRP_Msk

#define	CAN_BTR_TS1_Pos (16U)

#define	CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1 CAN_BTR_TS1_Msk

#define	CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS2_Pos (20U)

#define	CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2 CAN_BTR_TS2_Msk

#define	CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_SJW_Pos (24U)

#define	CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW CAN_BTR_SJW_Msk

#define	CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_LBKM_Pos (30U)

#define	CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)

#define	CAN_BTR_LBKM CAN_BTR_LBKM_Msk

#define	CAN_BTR_SILM_Pos (31U)

#define	CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)

#define	CAN_BTR_SILM CAN_BTR_SILM_Msk

#define	CAN_TI0R_TXRQ_Pos (0U)

#define	CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)

#define	CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk

#define	CAN_TI0R_RTR_Pos (1U)

#define	CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)

#define	CAN_TI0R_RTR CAN_TI0R_RTR_Msk

#define	CAN_TI0R_IDE_Pos (2U)

#define	CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)

#define	CAN_TI0R_IDE CAN_TI0R_IDE_Msk

#define	CAN_TI0R_EXID_Pos (3U)

#define	CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)

#define	CAN_TI0R_EXID CAN_TI0R_EXID_Msk

#define	CAN_TI0R_STID_Pos (21U)

#define	CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)

#define	CAN_TI0R_STID CAN_TI0R_STID_Msk

#define	CAN_TDT0R_DLC_Pos (0U)

#define	CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)

#define	CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk

#define	CAN_TDT0R_TGT_Pos (8U)

#define	CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)

#define	CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk

#define	CAN_TDT0R_TIME_Pos (16U)

#define	CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)

#define	CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk

#define	CAN_TDL0R_DATA0_Pos (0U)

#define	CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)

#define	CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk

#define	CAN_TDL0R_DATA1_Pos (8U)

#define	CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)

#define	CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk

#define	CAN_TDL0R_DATA2_Pos (16U)

#define	CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)

#define	CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk

#define	CAN_TDL0R_DATA3_Pos (24U)

#define	CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)

#define	CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk

#define	CAN_TDH0R_DATA4_Pos (0U)

#define	CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)

#define	CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk

#define	CAN_TDH0R_DATA5_Pos (8U)

#define	CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)

#define	CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk

#define	CAN_TDH0R_DATA6_Pos (16U)

#define	CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)

#define	CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk

#define	CAN_TDH0R_DATA7_Pos (24U)

#define	CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)

#define	CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk

#define	CAN_TI1R_TXRQ_Pos (0U)

#define	CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)

#define	CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk

#define	CAN_TI1R_RTR_Pos (1U)

#define	CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)

#define	CAN_TI1R_RTR CAN_TI1R_RTR_Msk

#define	CAN_TI1R_IDE_Pos (2U)

#define	CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)

#define	CAN_TI1R_IDE CAN_TI1R_IDE_Msk

#define	CAN_TI1R_EXID_Pos (3U)

#define	CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)

#define	CAN_TI1R_EXID CAN_TI1R_EXID_Msk

#define	CAN_TI1R_STID_Pos (21U)

#define	CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)

#define	CAN_TI1R_STID CAN_TI1R_STID_Msk

#define	CAN_TDT1R_DLC_Pos (0U)

#define	CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)

#define	CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk

#define	CAN_TDT1R_TGT_Pos (8U)

#define	CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)

#define	CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk

#define	CAN_TDT1R_TIME_Pos (16U)

#define	CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)

#define	CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk

#define	CAN_TDL1R_DATA0_Pos (0U)

#define	CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)

#define	CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk

#define	CAN_TDL1R_DATA1_Pos (8U)

#define	CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)

#define	CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk

#define	CAN_TDL1R_DATA2_Pos (16U)

#define	CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)

#define	CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk

#define	CAN_TDL1R_DATA3_Pos (24U)

#define	CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)

#define	CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk

#define	CAN_TDH1R_DATA4_Pos (0U)

#define	CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)

#define	CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk

#define	CAN_TDH1R_DATA5_Pos (8U)

#define	CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)

#define	CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk

#define	CAN_TDH1R_DATA6_Pos (16U)

#define	CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)

#define	CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk

#define	CAN_TDH1R_DATA7_Pos (24U)

#define	CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)

#define	CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk

#define	CAN_TI2R_TXRQ_Pos (0U)

#define	CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)

#define	CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk

#define	CAN_TI2R_RTR_Pos (1U)

#define	CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)

#define	CAN_TI2R_RTR CAN_TI2R_RTR_Msk

#define	CAN_TI2R_IDE_Pos (2U)

#define	CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)

#define	CAN_TI2R_IDE CAN_TI2R_IDE_Msk

#define	CAN_TI2R_EXID_Pos (3U)

#define	CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)

#define	CAN_TI2R_EXID CAN_TI2R_EXID_Msk

#define	CAN_TI2R_STID_Pos (21U)

#define	CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)

#define	CAN_TI2R_STID CAN_TI2R_STID_Msk

#define	CAN_TDT2R_DLC_Pos (0U)

#define	CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)

#define	CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk

#define	CAN_TDT2R_TGT_Pos (8U)

#define	CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)

#define	CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk

#define	CAN_TDT2R_TIME_Pos (16U)

#define	CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)

#define	CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk

#define	CAN_TDL2R_DATA0_Pos (0U)

#define	CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)

#define	CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk

#define	CAN_TDL2R_DATA1_Pos (8U)

#define	CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)

#define	CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk

#define	CAN_TDL2R_DATA2_Pos (16U)

#define	CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)

#define	CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk

#define	CAN_TDL2R_DATA3_Pos (24U)

#define	CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)

#define	CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk

#define	CAN_TDH2R_DATA4_Pos (0U)

#define	CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)

#define	CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk

#define	CAN_TDH2R_DATA5_Pos (8U)

#define	CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)

#define	CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk

#define	CAN_TDH2R_DATA6_Pos (16U)

#define	CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)

#define	CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk

#define	CAN_TDH2R_DATA7_Pos (24U)

#define	CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)

#define	CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk

#define	CAN_RI0R_RTR_Pos (1U)

#define	CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)

#define	CAN_RI0R_RTR CAN_RI0R_RTR_Msk

#define	CAN_RI0R_IDE_Pos (2U)

#define	CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)

#define	CAN_RI0R_IDE CAN_RI0R_IDE_Msk

#define	CAN_RI0R_EXID_Pos (3U)

#define	CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)

#define	CAN_RI0R_EXID CAN_RI0R_EXID_Msk

#define	CAN_RI0R_STID_Pos (21U)

#define	CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)

#define	CAN_RI0R_STID CAN_RI0R_STID_Msk

#define	CAN_RDT0R_DLC_Pos (0U)

#define	CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)

#define	CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk

#define	CAN_RDT0R_FMI_Pos (8U)

#define	CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)

#define	CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk

#define	CAN_RDT0R_TIME_Pos (16U)

#define	CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)

#define	CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk

#define	CAN_RDL0R_DATA0_Pos (0U)

#define	CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)

#define	CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk

#define	CAN_RDL0R_DATA1_Pos (8U)

#define	CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)

#define	CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk

#define	CAN_RDL0R_DATA2_Pos (16U)

#define	CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)

#define	CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk

#define	CAN_RDL0R_DATA3_Pos (24U)

#define	CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)

#define	CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk

#define	CAN_RDH0R_DATA4_Pos (0U)

#define	CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)

#define	CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk

#define	CAN_RDH0R_DATA5_Pos (8U)

#define	CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)

#define	CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk

#define	CAN_RDH0R_DATA6_Pos (16U)

#define	CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)

#define	CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk

#define	CAN_RDH0R_DATA7_Pos (24U)

#define	CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)

#define	CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk

#define	CAN_RI1R_RTR_Pos (1U)

#define	CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)

#define	CAN_RI1R_RTR CAN_RI1R_RTR_Msk

#define	CAN_RI1R_IDE_Pos (2U)

#define	CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)

#define	CAN_RI1R_IDE CAN_RI1R_IDE_Msk

#define	CAN_RI1R_EXID_Pos (3U)

#define	CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)

#define	CAN_RI1R_EXID CAN_RI1R_EXID_Msk

#define	CAN_RI1R_STID_Pos (21U)

#define	CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)

#define	CAN_RI1R_STID CAN_RI1R_STID_Msk

#define	CAN_RDT1R_DLC_Pos (0U)

#define	CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)

#define	CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk

#define	CAN_RDT1R_FMI_Pos (8U)

#define	CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)

#define	CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk

#define	CAN_RDT1R_TIME_Pos (16U)

#define	CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)

#define	CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk

#define	CAN_RDL1R_DATA0_Pos (0U)

#define	CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)

#define	CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk

#define	CAN_RDL1R_DATA1_Pos (8U)

#define	CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)

#define	CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk

#define	CAN_RDL1R_DATA2_Pos (16U)

#define	CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)

#define	CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk

#define	CAN_RDL1R_DATA3_Pos (24U)

#define	CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)

#define	CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk

#define	CAN_RDH1R_DATA4_Pos (0U)

#define	CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)

#define	CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk

#define	CAN_RDH1R_DATA5_Pos (8U)

#define	CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)

#define	CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk

#define	CAN_RDH1R_DATA6_Pos (16U)

#define	CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)

#define	CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk

#define	CAN_RDH1R_DATA7_Pos (24U)

#define	CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)

#define	CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk

#define	CAN_FMR_FINIT_Pos (0U)

#define	CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)

#define	CAN_FMR_FINIT CAN_FMR_FINIT_Msk

#define	CAN_FM1R_FBM_Pos (0U)

#define	CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)

#define	CAN_FM1R_FBM CAN_FM1R_FBM_Msk

#define	CAN_FM1R_FBM0_Pos (0U)

#define	CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)

#define	CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk

#define	CAN_FM1R_FBM1_Pos (1U)

#define	CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)

#define	CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk

#define	CAN_FM1R_FBM2_Pos (2U)

#define	CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)

#define	CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk

#define	CAN_FM1R_FBM3_Pos (3U)

#define	CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)

#define	CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk

#define	CAN_FM1R_FBM4_Pos (4U)

#define	CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)

#define	CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk

#define	CAN_FM1R_FBM5_Pos (5U)

#define	CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)

#define	CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk

#define	CAN_FM1R_FBM6_Pos (6U)

#define	CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)

#define	CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk

#define	CAN_FM1R_FBM7_Pos (7U)

#define	CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)

#define	CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk

#define	CAN_FM1R_FBM8_Pos (8U)

#define	CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)

#define	CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk

#define	CAN_FM1R_FBM9_Pos (9U)

#define	CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)

#define	CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk

#define	CAN_FM1R_FBM10_Pos (10U)

#define	CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)

#define	CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk

#define	CAN_FM1R_FBM11_Pos (11U)

#define	CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)

#define	CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk

#define	CAN_FM1R_FBM12_Pos (12U)

#define	CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)

#define	CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk

#define	CAN_FM1R_FBM13_Pos (13U)

#define	CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)

#define	CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk

#define	CAN_FS1R_FSC_Pos (0U)

#define	CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)

#define	CAN_FS1R_FSC CAN_FS1R_FSC_Msk

#define	CAN_FS1R_FSC0_Pos (0U)

#define	CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)

#define	CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk

#define	CAN_FS1R_FSC1_Pos (1U)

#define	CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)

#define	CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk

#define	CAN_FS1R_FSC2_Pos (2U)

#define	CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)

#define	CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk

#define	CAN_FS1R_FSC3_Pos (3U)

#define	CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)

#define	CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk

#define	CAN_FS1R_FSC4_Pos (4U)

#define	CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)

#define	CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk

#define	CAN_FS1R_FSC5_Pos (5U)

#define	CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)

#define	CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk

#define	CAN_FS1R_FSC6_Pos (6U)

#define	CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)

#define	CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk

#define	CAN_FS1R_FSC7_Pos (7U)

#define	CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)

#define	CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk

#define	CAN_FS1R_FSC8_Pos (8U)

#define	CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)

#define	CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk

#define	CAN_FS1R_FSC9_Pos (9U)

#define	CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)

#define	CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk

#define	CAN_FS1R_FSC10_Pos (10U)

#define	CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)

#define	CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk

#define	CAN_FS1R_FSC11_Pos (11U)

#define	CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)

#define	CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk

#define	CAN_FS1R_FSC12_Pos (12U)

#define	CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)

#define	CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk

#define	CAN_FS1R_FSC13_Pos (13U)

#define	CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)

#define	CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk

#define	CAN_FFA1R_FFA_Pos (0U)

#define	CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)

#define	CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk

#define	CAN_FFA1R_FFA0_Pos (0U)

#define	CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)

#define	CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk

#define	CAN_FFA1R_FFA1_Pos (1U)

#define	CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)

#define	CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk

#define	CAN_FFA1R_FFA2_Pos (2U)

#define	CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)

#define	CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk

#define	CAN_FFA1R_FFA3_Pos (3U)

#define	CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)

#define	CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk

#define	CAN_FFA1R_FFA4_Pos (4U)

#define	CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)

#define	CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk

#define	CAN_FFA1R_FFA5_Pos (5U)

#define	CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)

#define	CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk

#define	CAN_FFA1R_FFA6_Pos (6U)

#define	CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)

#define	CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk

#define	CAN_FFA1R_FFA7_Pos (7U)

#define	CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)

#define	CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk

#define	CAN_FFA1R_FFA8_Pos (8U)

#define	CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)

#define	CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk

#define	CAN_FFA1R_FFA9_Pos (9U)

#define	CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)

#define	CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk

#define	CAN_FFA1R_FFA10_Pos (10U)

#define	CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)

#define	CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk

#define	CAN_FFA1R_FFA11_Pos (11U)

#define	CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)

#define	CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk

#define	CAN_FFA1R_FFA12_Pos (12U)

#define	CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)

#define	CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk

#define	CAN_FFA1R_FFA13_Pos (13U)

#define	CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)

#define	CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk

#define	CAN_FA1R_FACT_Pos (0U)

#define	CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)

#define	CAN_FA1R_FACT CAN_FA1R_FACT_Msk

#define	CAN_FA1R_FACT0_Pos (0U)

#define	CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)

#define	CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk

#define	CAN_FA1R_FACT1_Pos (1U)

#define	CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)

#define	CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk

#define	CAN_FA1R_FACT2_Pos (2U)

#define	CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)

#define	CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk

#define	CAN_FA1R_FACT3_Pos (3U)

#define	CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)

#define	CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk

#define	CAN_FA1R_FACT4_Pos (4U)

#define	CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)

#define	CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk

#define	CAN_FA1R_FACT5_Pos (5U)

#define	CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)

#define	CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk

#define	CAN_FA1R_FACT6_Pos (6U)

#define	CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)

#define	CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk

#define	CAN_FA1R_FACT7_Pos (7U)

#define	CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)

#define	CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk

#define	CAN_FA1R_FACT8_Pos (8U)

#define	CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)

#define	CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk

#define	CAN_FA1R_FACT9_Pos (9U)

#define	CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)

#define	CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk

#define	CAN_FA1R_FACT10_Pos (10U)

#define	CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)

#define	CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk

#define	CAN_FA1R_FACT11_Pos (11U)

#define	CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)

#define	CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk

#define	CAN_FA1R_FACT12_Pos (12U)

#define	CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)

#define	CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk

#define	CAN_FA1R_FACT13_Pos (13U)

#define	CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)

#define	CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk

#define	CAN_F0R1_FB0_Pos (0U)

#define	CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)

#define	CAN_F0R1_FB0 CAN_F0R1_FB0_Msk

#define	CAN_F0R1_FB1_Pos (1U)

#define	CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)

#define	CAN_F0R1_FB1 CAN_F0R1_FB1_Msk

#define	CAN_F0R1_FB2_Pos (2U)

#define	CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)

#define	CAN_F0R1_FB2 CAN_F0R1_FB2_Msk

#define	CAN_F0R1_FB3_Pos (3U)

#define	CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)

#define	CAN_F0R1_FB3 CAN_F0R1_FB3_Msk

#define	CAN_F0R1_FB4_Pos (4U)

#define	CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)

#define	CAN_F0R1_FB4 CAN_F0R1_FB4_Msk

#define	CAN_F0R1_FB5_Pos (5U)

#define	CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)

#define	CAN_F0R1_FB5 CAN_F0R1_FB5_Msk

#define	CAN_F0R1_FB6_Pos (6U)

#define	CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)

#define	CAN_F0R1_FB6 CAN_F0R1_FB6_Msk

#define	CAN_F0R1_FB7_Pos (7U)

#define	CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)

#define	CAN_F0R1_FB7 CAN_F0R1_FB7_Msk

#define	CAN_F0R1_FB8_Pos (8U)

#define	CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)

#define	CAN_F0R1_FB8 CAN_F0R1_FB8_Msk

#define	CAN_F0R1_FB9_Pos (9U)

#define	CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)

#define	CAN_F0R1_FB9 CAN_F0R1_FB9_Msk

#define	CAN_F0R1_FB10_Pos (10U)

#define	CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)

#define	CAN_F0R1_FB10 CAN_F0R1_FB10_Msk

#define	CAN_F0R1_FB11_Pos (11U)

#define	CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)

#define	CAN_F0R1_FB11 CAN_F0R1_FB11_Msk

#define	CAN_F0R1_FB12_Pos (12U)

#define	CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)

#define	CAN_F0R1_FB12 CAN_F0R1_FB12_Msk

#define	CAN_F0R1_FB13_Pos (13U)

#define	CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)

#define	CAN_F0R1_FB13 CAN_F0R1_FB13_Msk

#define	CAN_F0R1_FB14_Pos (14U)

#define	CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)

#define	CAN_F0R1_FB14 CAN_F0R1_FB14_Msk

#define	CAN_F0R1_FB15_Pos (15U)

#define	CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)

#define	CAN_F0R1_FB15 CAN_F0R1_FB15_Msk

#define	CAN_F0R1_FB16_Pos (16U)

#define	CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)

#define	CAN_F0R1_FB16 CAN_F0R1_FB16_Msk

#define	CAN_F0R1_FB17_Pos (17U)

#define	CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)

#define	CAN_F0R1_FB17 CAN_F0R1_FB17_Msk

#define	CAN_F0R1_FB18_Pos (18U)

#define	CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)

#define	CAN_F0R1_FB18 CAN_F0R1_FB18_Msk

#define	CAN_F0R1_FB19_Pos (19U)

#define	CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)

#define	CAN_F0R1_FB19 CAN_F0R1_FB19_Msk

#define	CAN_F0R1_FB20_Pos (20U)

#define	CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)

#define	CAN_F0R1_FB20 CAN_F0R1_FB20_Msk

#define	CAN_F0R1_FB21_Pos (21U)

#define	CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)

#define	CAN_F0R1_FB21 CAN_F0R1_FB21_Msk

#define	CAN_F0R1_FB22_Pos (22U)

#define	CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)

#define	CAN_F0R1_FB22 CAN_F0R1_FB22_Msk

#define	CAN_F0R1_FB23_Pos (23U)

#define	CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)

#define	CAN_F0R1_FB23 CAN_F0R1_FB23_Msk

#define	CAN_F0R1_FB24_Pos (24U)

#define	CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)

#define	CAN_F0R1_FB24 CAN_F0R1_FB24_Msk

#define	CAN_F0R1_FB25_Pos (25U)

#define	CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)

#define	CAN_F0R1_FB25 CAN_F0R1_FB25_Msk

#define	CAN_F0R1_FB26_Pos (26U)

#define	CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)

#define	CAN_F0R1_FB26 CAN_F0R1_FB26_Msk

#define	CAN_F0R1_FB27_Pos (27U)

#define	CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)

#define	CAN_F0R1_FB27 CAN_F0R1_FB27_Msk

#define	CAN_F0R1_FB28_Pos (28U)

#define	CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)

#define	CAN_F0R1_FB28 CAN_F0R1_FB28_Msk

#define	CAN_F0R1_FB29_Pos (29U)

#define	CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)

#define	CAN_F0R1_FB29 CAN_F0R1_FB29_Msk

#define	CAN_F0R1_FB30_Pos (30U)

#define	CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)

#define	CAN_F0R1_FB30 CAN_F0R1_FB30_Msk

#define	CAN_F0R1_FB31_Pos (31U)

#define	CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)

#define	CAN_F0R1_FB31 CAN_F0R1_FB31_Msk

#define	CAN_F1R1_FB0_Pos (0U)

#define	CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)

#define	CAN_F1R1_FB0 CAN_F1R1_FB0_Msk

#define	CAN_F1R1_FB1_Pos (1U)

#define	CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)

#define	CAN_F1R1_FB1 CAN_F1R1_FB1_Msk

#define	CAN_F1R1_FB2_Pos (2U)

#define	CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)

#define	CAN_F1R1_FB2 CAN_F1R1_FB2_Msk

#define	CAN_F1R1_FB3_Pos (3U)

#define	CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)

#define	CAN_F1R1_FB3 CAN_F1R1_FB3_Msk

#define	CAN_F1R1_FB4_Pos (4U)

#define	CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)

#define	CAN_F1R1_FB4 CAN_F1R1_FB4_Msk

#define	CAN_F1R1_FB5_Pos (5U)

#define	CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)

#define	CAN_F1R1_FB5 CAN_F1R1_FB5_Msk

#define	CAN_F1R1_FB6_Pos (6U)

#define	CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)

#define	CAN_F1R1_FB6 CAN_F1R1_FB6_Msk

#define	CAN_F1R1_FB7_Pos (7U)

#define	CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)

#define	CAN_F1R1_FB7 CAN_F1R1_FB7_Msk

#define	CAN_F1R1_FB8_Pos (8U)

#define	CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)

#define	CAN_F1R1_FB8 CAN_F1R1_FB8_Msk

#define	CAN_F1R1_FB9_Pos (9U)

#define	CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)

#define	CAN_F1R1_FB9 CAN_F1R1_FB9_Msk

#define	CAN_F1R1_FB10_Pos (10U)

#define	CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)

#define	CAN_F1R1_FB10 CAN_F1R1_FB10_Msk

#define	CAN_F1R1_FB11_Pos (11U)

#define	CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)

#define	CAN_F1R1_FB11 CAN_F1R1_FB11_Msk

#define	CAN_F1R1_FB12_Pos (12U)

#define	CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)

#define	CAN_F1R1_FB12 CAN_F1R1_FB12_Msk

#define	CAN_F1R1_FB13_Pos (13U)

#define	CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)

#define	CAN_F1R1_FB13 CAN_F1R1_FB13_Msk

#define	CAN_F1R1_FB14_Pos (14U)

#define	CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)

#define	CAN_F1R1_FB14 CAN_F1R1_FB14_Msk

#define	CAN_F1R1_FB15_Pos (15U)

#define	CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)

#define	CAN_F1R1_FB15 CAN_F1R1_FB15_Msk

#define	CAN_F1R1_FB16_Pos (16U)

#define	CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)

#define	CAN_F1R1_FB16 CAN_F1R1_FB16_Msk

#define	CAN_F1R1_FB17_Pos (17U)

#define	CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)

#define	CAN_F1R1_FB17 CAN_F1R1_FB17_Msk

#define	CAN_F1R1_FB18_Pos (18U)

#define	CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)

#define	CAN_F1R1_FB18 CAN_F1R1_FB18_Msk

#define	CAN_F1R1_FB19_Pos (19U)

#define	CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)

#define	CAN_F1R1_FB19 CAN_F1R1_FB19_Msk

#define	CAN_F1R1_FB20_Pos (20U)

#define	CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)

#define	CAN_F1R1_FB20 CAN_F1R1_FB20_Msk

#define	CAN_F1R1_FB21_Pos (21U)

#define	CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)

#define	CAN_F1R1_FB21 CAN_F1R1_FB21_Msk

#define	CAN_F1R1_FB22_Pos (22U)

#define	CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)

#define	CAN_F1R1_FB22 CAN_F1R1_FB22_Msk

#define	CAN_F1R1_FB23_Pos (23U)

#define	CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)

#define	CAN_F1R1_FB23 CAN_F1R1_FB23_Msk

#define	CAN_F1R1_FB24_Pos (24U)

#define	CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)

#define	CAN_F1R1_FB24 CAN_F1R1_FB24_Msk

#define	CAN_F1R1_FB25_Pos (25U)

#define	CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)

#define	CAN_F1R1_FB25 CAN_F1R1_FB25_Msk

#define	CAN_F1R1_FB26_Pos (26U)

#define	CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)

#define	CAN_F1R1_FB26 CAN_F1R1_FB26_Msk

#define	CAN_F1R1_FB27_Pos (27U)

#define	CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)

#define	CAN_F1R1_FB27 CAN_F1R1_FB27_Msk

#define	CAN_F1R1_FB28_Pos (28U)

#define	CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)

#define	CAN_F1R1_FB28 CAN_F1R1_FB28_Msk

#define	CAN_F1R1_FB29_Pos (29U)

#define	CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)

#define	CAN_F1R1_FB29 CAN_F1R1_FB29_Msk

#define	CAN_F1R1_FB30_Pos (30U)

#define	CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)

#define	CAN_F1R1_FB30 CAN_F1R1_FB30_Msk

#define	CAN_F1R1_FB31_Pos (31U)

#define	CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)

#define	CAN_F1R1_FB31 CAN_F1R1_FB31_Msk

#define	CAN_F2R1_FB0_Pos (0U)

#define	CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)

#define	CAN_F2R1_FB0 CAN_F2R1_FB0_Msk

#define	CAN_F2R1_FB1_Pos (1U)

#define	CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)

#define	CAN_F2R1_FB1 CAN_F2R1_FB1_Msk

#define	CAN_F2R1_FB2_Pos (2U)

#define	CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)

#define	CAN_F2R1_FB2 CAN_F2R1_FB2_Msk

#define	CAN_F2R1_FB3_Pos (3U)

#define	CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)

#define	CAN_F2R1_FB3 CAN_F2R1_FB3_Msk

#define	CAN_F2R1_FB4_Pos (4U)

#define	CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)

#define	CAN_F2R1_FB4 CAN_F2R1_FB4_Msk

#define	CAN_F2R1_FB5_Pos (5U)

#define	CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)

#define	CAN_F2R1_FB5 CAN_F2R1_FB5_Msk

#define	CAN_F2R1_FB6_Pos (6U)

#define	CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)

#define	CAN_F2R1_FB6 CAN_F2R1_FB6_Msk

#define	CAN_F2R1_FB7_Pos (7U)

#define	CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)

#define	CAN_F2R1_FB7 CAN_F2R1_FB7_Msk

#define	CAN_F2R1_FB8_Pos (8U)

#define	CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)

#define	CAN_F2R1_FB8 CAN_F2R1_FB8_Msk

#define	CAN_F2R1_FB9_Pos (9U)

#define	CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)

#define	CAN_F2R1_FB9 CAN_F2R1_FB9_Msk

#define	CAN_F2R1_FB10_Pos (10U)

#define	CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)

#define	CAN_F2R1_FB10 CAN_F2R1_FB10_Msk

#define	CAN_F2R1_FB11_Pos (11U)

#define	CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)

#define	CAN_F2R1_FB11 CAN_F2R1_FB11_Msk

#define	CAN_F2R1_FB12_Pos (12U)

#define	CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)

#define	CAN_F2R1_FB12 CAN_F2R1_FB12_Msk

#define	CAN_F2R1_FB13_Pos (13U)

#define	CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)

#define	CAN_F2R1_FB13 CAN_F2R1_FB13_Msk

#define	CAN_F2R1_FB14_Pos (14U)

#define	CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)

#define	CAN_F2R1_FB14 CAN_F2R1_FB14_Msk

#define	CAN_F2R1_FB15_Pos (15U)

#define	CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)

#define	CAN_F2R1_FB15 CAN_F2R1_FB15_Msk

#define	CAN_F2R1_FB16_Pos (16U)

#define	CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)

#define	CAN_F2R1_FB16 CAN_F2R1_FB16_Msk

#define	CAN_F2R1_FB17_Pos (17U)

#define	CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)

#define	CAN_F2R1_FB17 CAN_F2R1_FB17_Msk

#define	CAN_F2R1_FB18_Pos (18U)

#define	CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)

#define	CAN_F2R1_FB18 CAN_F2R1_FB18_Msk

#define	CAN_F2R1_FB19_Pos (19U)

#define	CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)

#define	CAN_F2R1_FB19 CAN_F2R1_FB19_Msk

#define	CAN_F2R1_FB20_Pos (20U)

#define	CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)

#define	CAN_F2R1_FB20 CAN_F2R1_FB20_Msk

#define	CAN_F2R1_FB21_Pos (21U)

#define	CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)

#define	CAN_F2R1_FB21 CAN_F2R1_FB21_Msk

#define	CAN_F2R1_FB22_Pos (22U)

#define	CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)

#define	CAN_F2R1_FB22 CAN_F2R1_FB22_Msk

#define	CAN_F2R1_FB23_Pos (23U)

#define	CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)

#define	CAN_F2R1_FB23 CAN_F2R1_FB23_Msk

#define	CAN_F2R1_FB24_Pos (24U)

#define	CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)

#define	CAN_F2R1_FB24 CAN_F2R1_FB24_Msk

#define	CAN_F2R1_FB25_Pos (25U)

#define	CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)

#define	CAN_F2R1_FB25 CAN_F2R1_FB25_Msk

#define	CAN_F2R1_FB26_Pos (26U)

#define	CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)

#define	CAN_F2R1_FB26 CAN_F2R1_FB26_Msk

#define	CAN_F2R1_FB27_Pos (27U)

#define	CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)

#define	CAN_F2R1_FB27 CAN_F2R1_FB27_Msk

#define	CAN_F2R1_FB28_Pos (28U)

#define	CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)

#define	CAN_F2R1_FB28 CAN_F2R1_FB28_Msk

#define	CAN_F2R1_FB29_Pos (29U)

#define	CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)

#define	CAN_F2R1_FB29 CAN_F2R1_FB29_Msk

#define	CAN_F2R1_FB30_Pos (30U)

#define	CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)

#define	CAN_F2R1_FB30 CAN_F2R1_FB30_Msk

#define	CAN_F2R1_FB31_Pos (31U)

#define	CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)

#define	CAN_F2R1_FB31 CAN_F2R1_FB31_Msk

#define	CAN_F3R1_FB0_Pos (0U)

#define	CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)

#define	CAN_F3R1_FB0 CAN_F3R1_FB0_Msk

#define	CAN_F3R1_FB1_Pos (1U)

#define	CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)

#define	CAN_F3R1_FB1 CAN_F3R1_FB1_Msk

#define	CAN_F3R1_FB2_Pos (2U)

#define	CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)

#define	CAN_F3R1_FB2 CAN_F3R1_FB2_Msk

#define	CAN_F3R1_FB3_Pos (3U)

#define	CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)

#define	CAN_F3R1_FB3 CAN_F3R1_FB3_Msk

#define	CAN_F3R1_FB4_Pos (4U)

#define	CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)

#define	CAN_F3R1_FB4 CAN_F3R1_FB4_Msk

#define	CAN_F3R1_FB5_Pos (5U)

#define	CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)

#define	CAN_F3R1_FB5 CAN_F3R1_FB5_Msk

#define	CAN_F3R1_FB6_Pos (6U)

#define	CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)

#define	CAN_F3R1_FB6 CAN_F3R1_FB6_Msk

#define	CAN_F3R1_FB7_Pos (7U)

#define	CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)

#define	CAN_F3R1_FB7 CAN_F3R1_FB7_Msk

#define	CAN_F3R1_FB8_Pos (8U)

#define	CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)

#define	CAN_F3R1_FB8 CAN_F3R1_FB8_Msk

#define	CAN_F3R1_FB9_Pos (9U)

#define	CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)

#define	CAN_F3R1_FB9 CAN_F3R1_FB9_Msk

#define	CAN_F3R1_FB10_Pos (10U)

#define	CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)

#define	CAN_F3R1_FB10 CAN_F3R1_FB10_Msk

#define	CAN_F3R1_FB11_Pos (11U)

#define	CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)

#define	CAN_F3R1_FB11 CAN_F3R1_FB11_Msk

#define	CAN_F3R1_FB12_Pos (12U)

#define	CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)

#define	CAN_F3R1_FB12 CAN_F3R1_FB12_Msk

#define	CAN_F3R1_FB13_Pos (13U)

#define	CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)

#define	CAN_F3R1_FB13 CAN_F3R1_FB13_Msk

#define	CAN_F3R1_FB14_Pos (14U)

#define	CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)

#define	CAN_F3R1_FB14 CAN_F3R1_FB14_Msk

#define	CAN_F3R1_FB15_Pos (15U)

#define	CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)

#define	CAN_F3R1_FB15 CAN_F3R1_FB15_Msk

#define	CAN_F3R1_FB16_Pos (16U)

#define	CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)

#define	CAN_F3R1_FB16 CAN_F3R1_FB16_Msk

#define	CAN_F3R1_FB17_Pos (17U)

#define	CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)

#define	CAN_F3R1_FB17 CAN_F3R1_FB17_Msk

#define	CAN_F3R1_FB18_Pos (18U)

#define	CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)

#define	CAN_F3R1_FB18 CAN_F3R1_FB18_Msk

#define	CAN_F3R1_FB19_Pos (19U)

#define	CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)

#define	CAN_F3R1_FB19 CAN_F3R1_FB19_Msk

#define	CAN_F3R1_FB20_Pos (20U)

#define	CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)

#define	CAN_F3R1_FB20 CAN_F3R1_FB20_Msk

#define	CAN_F3R1_FB21_Pos (21U)

#define	CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)

#define	CAN_F3R1_FB21 CAN_F3R1_FB21_Msk

#define	CAN_F3R1_FB22_Pos (22U)

#define	CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)

#define	CAN_F3R1_FB22 CAN_F3R1_FB22_Msk

#define	CAN_F3R1_FB23_Pos (23U)

#define	CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)

#define	CAN_F3R1_FB23 CAN_F3R1_FB23_Msk

#define	CAN_F3R1_FB24_Pos (24U)

#define	CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)

#define	CAN_F3R1_FB24 CAN_F3R1_FB24_Msk

#define	CAN_F3R1_FB25_Pos (25U)

#define	CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)

#define	CAN_F3R1_FB25 CAN_F3R1_FB25_Msk

#define	CAN_F3R1_FB26_Pos (26U)

#define	CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)

#define	CAN_F3R1_FB26 CAN_F3R1_FB26_Msk

#define	CAN_F3R1_FB27_Pos (27U)

#define	CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)

#define	CAN_F3R1_FB27 CAN_F3R1_FB27_Msk

#define	CAN_F3R1_FB28_Pos (28U)

#define	CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)

#define	CAN_F3R1_FB28 CAN_F3R1_FB28_Msk

#define	CAN_F3R1_FB29_Pos (29U)

#define	CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)

#define	CAN_F3R1_FB29 CAN_F3R1_FB29_Msk

#define	CAN_F3R1_FB30_Pos (30U)

#define	CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)

#define	CAN_F3R1_FB30 CAN_F3R1_FB30_Msk

#define	CAN_F3R1_FB31_Pos (31U)

#define	CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)

#define	CAN_F3R1_FB31 CAN_F3R1_FB31_Msk

#define	CAN_F4R1_FB0_Pos (0U)

#define	CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)

#define	CAN_F4R1_FB0 CAN_F4R1_FB0_Msk

#define	CAN_F4R1_FB1_Pos (1U)

#define	CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)

#define	CAN_F4R1_FB1 CAN_F4R1_FB1_Msk

#define	CAN_F4R1_FB2_Pos (2U)

#define	CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)

#define	CAN_F4R1_FB2 CAN_F4R1_FB2_Msk

#define	CAN_F4R1_FB3_Pos (3U)

#define	CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)

#define	CAN_F4R1_FB3 CAN_F4R1_FB3_Msk

#define	CAN_F4R1_FB4_Pos (4U)

#define	CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)

#define	CAN_F4R1_FB4 CAN_F4R1_FB4_Msk

#define	CAN_F4R1_FB5_Pos (5U)

#define	CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)

#define	CAN_F4R1_FB5 CAN_F4R1_FB5_Msk

#define	CAN_F4R1_FB6_Pos (6U)

#define	CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)

#define	CAN_F4R1_FB6 CAN_F4R1_FB6_Msk

#define	CAN_F4R1_FB7_Pos (7U)

#define	CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)

#define	CAN_F4R1_FB7 CAN_F4R1_FB7_Msk

#define	CAN_F4R1_FB8_Pos (8U)

#define	CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)

#define	CAN_F4R1_FB8 CAN_F4R1_FB8_Msk

#define	CAN_F4R1_FB9_Pos (9U)

#define	CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)

#define	CAN_F4R1_FB9 CAN_F4R1_FB9_Msk

#define	CAN_F4R1_FB10_Pos (10U)

#define	CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)

#define	CAN_F4R1_FB10 CAN_F4R1_FB10_Msk

#define	CAN_F4R1_FB11_Pos (11U)

#define	CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)

#define	CAN_F4R1_FB11 CAN_F4R1_FB11_Msk

#define	CAN_F4R1_FB12_Pos (12U)

#define	CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)

#define	CAN_F4R1_FB12 CAN_F4R1_FB12_Msk

#define	CAN_F4R1_FB13_Pos (13U)

#define	CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)

#define	CAN_F4R1_FB13 CAN_F4R1_FB13_Msk

#define	CAN_F4R1_FB14_Pos (14U)

#define	CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)

#define	CAN_F4R1_FB14 CAN_F4R1_FB14_Msk

#define	CAN_F4R1_FB15_Pos (15U)

#define	CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)

#define	CAN_F4R1_FB15 CAN_F4R1_FB15_Msk

#define	CAN_F4R1_FB16_Pos (16U)

#define	CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)

#define	CAN_F4R1_FB16 CAN_F4R1_FB16_Msk

#define	CAN_F4R1_FB17_Pos (17U)

#define	CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)

#define	CAN_F4R1_FB17 CAN_F4R1_FB17_Msk

#define	CAN_F4R1_FB18_Pos (18U)

#define	CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)

#define	CAN_F4R1_FB18 CAN_F4R1_FB18_Msk

#define	CAN_F4R1_FB19_Pos (19U)

#define	CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)

#define	CAN_F4R1_FB19 CAN_F4R1_FB19_Msk

#define	CAN_F4R1_FB20_Pos (20U)

#define	CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)

#define	CAN_F4R1_FB20 CAN_F4R1_FB20_Msk

#define	CAN_F4R1_FB21_Pos (21U)

#define	CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)

#define	CAN_F4R1_FB21 CAN_F4R1_FB21_Msk

#define	CAN_F4R1_FB22_Pos (22U)

#define	CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)

#define	CAN_F4R1_FB22 CAN_F4R1_FB22_Msk

#define	CAN_F4R1_FB23_Pos (23U)

#define	CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)

#define	CAN_F4R1_FB23 CAN_F4R1_FB23_Msk

#define	CAN_F4R1_FB24_Pos (24U)

#define	CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)

#define	CAN_F4R1_FB24 CAN_F4R1_FB24_Msk

#define	CAN_F4R1_FB25_Pos (25U)

#define	CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)

#define	CAN_F4R1_FB25 CAN_F4R1_FB25_Msk

#define	CAN_F4R1_FB26_Pos (26U)

#define	CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)

#define	CAN_F4R1_FB26 CAN_F4R1_FB26_Msk

#define	CAN_F4R1_FB27_Pos (27U)

#define	CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)

#define	CAN_F4R1_FB27 CAN_F4R1_FB27_Msk

#define	CAN_F4R1_FB28_Pos (28U)

#define	CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)

#define	CAN_F4R1_FB28 CAN_F4R1_FB28_Msk

#define	CAN_F4R1_FB29_Pos (29U)

#define	CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)

#define	CAN_F4R1_FB29 CAN_F4R1_FB29_Msk

#define	CAN_F4R1_FB30_Pos (30U)

#define	CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)

#define	CAN_F4R1_FB30 CAN_F4R1_FB30_Msk

#define	CAN_F4R1_FB31_Pos (31U)

#define	CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)

#define	CAN_F4R1_FB31 CAN_F4R1_FB31_Msk

#define	CAN_F5R1_FB0_Pos (0U)

#define	CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)

#define	CAN_F5R1_FB0 CAN_F5R1_FB0_Msk

#define	CAN_F5R1_FB1_Pos (1U)

#define	CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)

#define	CAN_F5R1_FB1 CAN_F5R1_FB1_Msk

#define	CAN_F5R1_FB2_Pos (2U)

#define	CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)

#define	CAN_F5R1_FB2 CAN_F5R1_FB2_Msk

#define	CAN_F5R1_FB3_Pos (3U)

#define	CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)

#define	CAN_F5R1_FB3 CAN_F5R1_FB3_Msk

#define	CAN_F5R1_FB4_Pos (4U)

#define	CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)

#define	CAN_F5R1_FB4 CAN_F5R1_FB4_Msk

#define	CAN_F5R1_FB5_Pos (5U)

#define	CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)

#define	CAN_F5R1_FB5 CAN_F5R1_FB5_Msk

#define	CAN_F5R1_FB6_Pos (6U)

#define	CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)

#define	CAN_F5R1_FB6 CAN_F5R1_FB6_Msk

#define	CAN_F5R1_FB7_Pos (7U)

#define	CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)

#define	CAN_F5R1_FB7 CAN_F5R1_FB7_Msk

#define	CAN_F5R1_FB8_Pos (8U)

#define	CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)

#define	CAN_F5R1_FB8 CAN_F5R1_FB8_Msk

#define	CAN_F5R1_FB9_Pos (9U)

#define	CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)

#define	CAN_F5R1_FB9 CAN_F5R1_FB9_Msk

#define	CAN_F5R1_FB10_Pos (10U)

#define	CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)

#define	CAN_F5R1_FB10 CAN_F5R1_FB10_Msk

#define	CAN_F5R1_FB11_Pos (11U)

#define	CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)

#define	CAN_F5R1_FB11 CAN_F5R1_FB11_Msk

#define	CAN_F5R1_FB12_Pos (12U)

#define	CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)

#define	CAN_F5R1_FB12 CAN_F5R1_FB12_Msk

#define	CAN_F5R1_FB13_Pos (13U)

#define	CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)

#define	CAN_F5R1_FB13 CAN_F5R1_FB13_Msk

#define	CAN_F5R1_FB14_Pos (14U)

#define	CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)

#define	CAN_F5R1_FB14 CAN_F5R1_FB14_Msk

#define	CAN_F5R1_FB15_Pos (15U)

#define	CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)

#define	CAN_F5R1_FB15 CAN_F5R1_FB15_Msk

#define	CAN_F5R1_FB16_Pos (16U)

#define	CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)

#define	CAN_F5R1_FB16 CAN_F5R1_FB16_Msk

#define	CAN_F5R1_FB17_Pos (17U)

#define	CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)

#define	CAN_F5R1_FB17 CAN_F5R1_FB17_Msk

#define	CAN_F5R1_FB18_Pos (18U)

#define	CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)

#define	CAN_F5R1_FB18 CAN_F5R1_FB18_Msk

#define	CAN_F5R1_FB19_Pos (19U)

#define	CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)

#define	CAN_F5R1_FB19 CAN_F5R1_FB19_Msk

#define	CAN_F5R1_FB20_Pos (20U)

#define	CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)

#define	CAN_F5R1_FB20 CAN_F5R1_FB20_Msk

#define	CAN_F5R1_FB21_Pos (21U)

#define	CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)

#define	CAN_F5R1_FB21 CAN_F5R1_FB21_Msk

#define	CAN_F5R1_FB22_Pos (22U)

#define	CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)

#define	CAN_F5R1_FB22 CAN_F5R1_FB22_Msk

#define	CAN_F5R1_FB23_Pos (23U)

#define	CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)

#define	CAN_F5R1_FB23 CAN_F5R1_FB23_Msk

#define	CAN_F5R1_FB24_Pos (24U)

#define	CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)

#define	CAN_F5R1_FB24 CAN_F5R1_FB24_Msk

#define	CAN_F5R1_FB25_Pos (25U)

#define	CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)

#define	CAN_F5R1_FB25 CAN_F5R1_FB25_Msk

#define	CAN_F5R1_FB26_Pos (26U)

#define	CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)

#define	CAN_F5R1_FB26 CAN_F5R1_FB26_Msk

#define	CAN_F5R1_FB27_Pos (27U)

#define	CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)

#define	CAN_F5R1_FB27 CAN_F5R1_FB27_Msk

#define	CAN_F5R1_FB28_Pos (28U)

#define	CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)

#define	CAN_F5R1_FB28 CAN_F5R1_FB28_Msk

#define	CAN_F5R1_FB29_Pos (29U)

#define	CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)

#define	CAN_F5R1_FB29 CAN_F5R1_FB29_Msk

#define	CAN_F5R1_FB30_Pos (30U)

#define	CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)

#define	CAN_F5R1_FB30 CAN_F5R1_FB30_Msk

#define	CAN_F5R1_FB31_Pos (31U)

#define	CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)

#define	CAN_F5R1_FB31 CAN_F5R1_FB31_Msk

#define	CAN_F6R1_FB0_Pos (0U)

#define	CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)

#define	CAN_F6R1_FB0 CAN_F6R1_FB0_Msk

#define	CAN_F6R1_FB1_Pos (1U)

#define	CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)

#define	CAN_F6R1_FB1 CAN_F6R1_FB1_Msk

#define	CAN_F6R1_FB2_Pos (2U)

#define	CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)

#define	CAN_F6R1_FB2 CAN_F6R1_FB2_Msk

#define	CAN_F6R1_FB3_Pos (3U)

#define	CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)

#define	CAN_F6R1_FB3 CAN_F6R1_FB3_Msk

#define	CAN_F6R1_FB4_Pos (4U)

#define	CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)

#define	CAN_F6R1_FB4 CAN_F6R1_FB4_Msk

#define	CAN_F6R1_FB5_Pos (5U)

#define	CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)

#define	CAN_F6R1_FB5 CAN_F6R1_FB5_Msk

#define	CAN_F6R1_FB6_Pos (6U)

#define	CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)

#define	CAN_F6R1_FB6 CAN_F6R1_FB6_Msk

#define	CAN_F6R1_FB7_Pos (7U)

#define	CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)

#define	CAN_F6R1_FB7 CAN_F6R1_FB7_Msk

#define	CAN_F6R1_FB8_Pos (8U)

#define	CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)

#define	CAN_F6R1_FB8 CAN_F6R1_FB8_Msk

#define	CAN_F6R1_FB9_Pos (9U)

#define	CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)

#define	CAN_F6R1_FB9 CAN_F6R1_FB9_Msk

#define	CAN_F6R1_FB10_Pos (10U)

#define	CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)

#define	CAN_F6R1_FB10 CAN_F6R1_FB10_Msk

#define	CAN_F6R1_FB11_Pos (11U)

#define	CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)

#define	CAN_F6R1_FB11 CAN_F6R1_FB11_Msk

#define	CAN_F6R1_FB12_Pos (12U)

#define	CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)

#define	CAN_F6R1_FB12 CAN_F6R1_FB12_Msk

#define	CAN_F6R1_FB13_Pos (13U)

#define	CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)

#define	CAN_F6R1_FB13 CAN_F6R1_FB13_Msk

#define	CAN_F6R1_FB14_Pos (14U)

#define	CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)

#define	CAN_F6R1_FB14 CAN_F6R1_FB14_Msk

#define	CAN_F6R1_FB15_Pos (15U)

#define	CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)

#define	CAN_F6R1_FB15 CAN_F6R1_FB15_Msk

#define	CAN_F6R1_FB16_Pos (16U)

#define	CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)

#define	CAN_F6R1_FB16 CAN_F6R1_FB16_Msk

#define	CAN_F6R1_FB17_Pos (17U)

#define	CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)

#define	CAN_F6R1_FB17 CAN_F6R1_FB17_Msk

#define	CAN_F6R1_FB18_Pos (18U)

#define	CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)

#define	CAN_F6R1_FB18 CAN_F6R1_FB18_Msk

#define	CAN_F6R1_FB19_Pos (19U)

#define	CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)

#define	CAN_F6R1_FB19 CAN_F6R1_FB19_Msk

#define	CAN_F6R1_FB20_Pos (20U)

#define	CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)

#define	CAN_F6R1_FB20 CAN_F6R1_FB20_Msk

#define	CAN_F6R1_FB21_Pos (21U)

#define	CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)

#define	CAN_F6R1_FB21 CAN_F6R1_FB21_Msk

#define	CAN_F6R1_FB22_Pos (22U)

#define	CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)

#define	CAN_F6R1_FB22 CAN_F6R1_FB22_Msk

#define	CAN_F6R1_FB23_Pos (23U)

#define	CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)

#define	CAN_F6R1_FB23 CAN_F6R1_FB23_Msk

#define	CAN_F6R1_FB24_Pos (24U)

#define	CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)

#define	CAN_F6R1_FB24 CAN_F6R1_FB24_Msk

#define	CAN_F6R1_FB25_Pos (25U)

#define	CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)

#define	CAN_F6R1_FB25 CAN_F6R1_FB25_Msk

#define	CAN_F6R1_FB26_Pos (26U)

#define	CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)

#define	CAN_F6R1_FB26 CAN_F6R1_FB26_Msk

#define	CAN_F6R1_FB27_Pos (27U)

#define	CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)

#define	CAN_F6R1_FB27 CAN_F6R1_FB27_Msk

#define	CAN_F6R1_FB28_Pos (28U)

#define	CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)

#define	CAN_F6R1_FB28 CAN_F6R1_FB28_Msk

#define	CAN_F6R1_FB29_Pos (29U)

#define	CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)

#define	CAN_F6R1_FB29 CAN_F6R1_FB29_Msk

#define	CAN_F6R1_FB30_Pos (30U)

#define	CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)

#define	CAN_F6R1_FB30 CAN_F6R1_FB30_Msk

#define	CAN_F6R1_FB31_Pos (31U)

#define	CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)

#define	CAN_F6R1_FB31 CAN_F6R1_FB31_Msk

#define	CAN_F7R1_FB0_Pos (0U)

#define	CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)

#define	CAN_F7R1_FB0 CAN_F7R1_FB0_Msk

#define	CAN_F7R1_FB1_Pos (1U)

#define	CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)

#define	CAN_F7R1_FB1 CAN_F7R1_FB1_Msk

#define	CAN_F7R1_FB2_Pos (2U)

#define	CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)

#define	CAN_F7R1_FB2 CAN_F7R1_FB2_Msk

#define	CAN_F7R1_FB3_Pos (3U)

#define	CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)

#define	CAN_F7R1_FB3 CAN_F7R1_FB3_Msk

#define	CAN_F7R1_FB4_Pos (4U)

#define	CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)

#define	CAN_F7R1_FB4 CAN_F7R1_FB4_Msk

#define	CAN_F7R1_FB5_Pos (5U)

#define	CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)

#define	CAN_F7R1_FB5 CAN_F7R1_FB5_Msk

#define	CAN_F7R1_FB6_Pos (6U)

#define	CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)

#define	CAN_F7R1_FB6 CAN_F7R1_FB6_Msk

#define	CAN_F7R1_FB7_Pos (7U)

#define	CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)

#define	CAN_F7R1_FB7 CAN_F7R1_FB7_Msk

#define	CAN_F7R1_FB8_Pos (8U)

#define	CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)

#define	CAN_F7R1_FB8 CAN_F7R1_FB8_Msk

#define	CAN_F7R1_FB9_Pos (9U)

#define	CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)

#define	CAN_F7R1_FB9 CAN_F7R1_FB9_Msk

#define	CAN_F7R1_FB10_Pos (10U)

#define	CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)

#define	CAN_F7R1_FB10 CAN_F7R1_FB10_Msk

#define	CAN_F7R1_FB11_Pos (11U)

#define	CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)

#define	CAN_F7R1_FB11 CAN_F7R1_FB11_Msk

#define	CAN_F7R1_FB12_Pos (12U)

#define	CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)

#define	CAN_F7R1_FB12 CAN_F7R1_FB12_Msk

#define	CAN_F7R1_FB13_Pos (13U)

#define	CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)

#define	CAN_F7R1_FB13 CAN_F7R1_FB13_Msk

#define	CAN_F7R1_FB14_Pos (14U)

#define	CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)

#define	CAN_F7R1_FB14 CAN_F7R1_FB14_Msk

#define	CAN_F7R1_FB15_Pos (15U)

#define	CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)

#define	CAN_F7R1_FB15 CAN_F7R1_FB15_Msk

#define	CAN_F7R1_FB16_Pos (16U)

#define	CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)

#define	CAN_F7R1_FB16 CAN_F7R1_FB16_Msk

#define	CAN_F7R1_FB17_Pos (17U)

#define	CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)

#define	CAN_F7R1_FB17 CAN_F7R1_FB17_Msk

#define	CAN_F7R1_FB18_Pos (18U)

#define	CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)

#define	CAN_F7R1_FB18 CAN_F7R1_FB18_Msk

#define	CAN_F7R1_FB19_Pos (19U)

#define	CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)

#define	CAN_F7R1_FB19 CAN_F7R1_FB19_Msk

#define	CAN_F7R1_FB20_Pos (20U)

#define	CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)

#define	CAN_F7R1_FB20 CAN_F7R1_FB20_Msk

#define	CAN_F7R1_FB21_Pos (21U)

#define	CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)

#define	CAN_F7R1_FB21 CAN_F7R1_FB21_Msk

#define	CAN_F7R1_FB22_Pos (22U)

#define	CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)

#define	CAN_F7R1_FB22 CAN_F7R1_FB22_Msk

#define	CAN_F7R1_FB23_Pos (23U)

#define	CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)

#define	CAN_F7R1_FB23 CAN_F7R1_FB23_Msk

#define	CAN_F7R1_FB24_Pos (24U)

#define	CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)

#define	CAN_F7R1_FB24 CAN_F7R1_FB24_Msk

#define	CAN_F7R1_FB25_Pos (25U)

#define	CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)

#define	CAN_F7R1_FB25 CAN_F7R1_FB25_Msk

#define	CAN_F7R1_FB26_Pos (26U)

#define	CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)

#define	CAN_F7R1_FB26 CAN_F7R1_FB26_Msk

#define	CAN_F7R1_FB27_Pos (27U)

#define	CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)

#define	CAN_F7R1_FB27 CAN_F7R1_FB27_Msk

#define	CAN_F7R1_FB28_Pos (28U)

#define	CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)

#define	CAN_F7R1_FB28 CAN_F7R1_FB28_Msk

#define	CAN_F7R1_FB29_Pos (29U)

#define	CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)

#define	CAN_F7R1_FB29 CAN_F7R1_FB29_Msk

#define	CAN_F7R1_FB30_Pos (30U)

#define	CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)

#define	CAN_F7R1_FB30 CAN_F7R1_FB30_Msk

#define	CAN_F7R1_FB31_Pos (31U)

#define	CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)

#define	CAN_F7R1_FB31 CAN_F7R1_FB31_Msk

#define	CAN_F8R1_FB0_Pos (0U)

#define	CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)

#define	CAN_F8R1_FB0 CAN_F8R1_FB0_Msk

#define	CAN_F8R1_FB1_Pos (1U)

#define	CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)

#define	CAN_F8R1_FB1 CAN_F8R1_FB1_Msk

#define	CAN_F8R1_FB2_Pos (2U)

#define	CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)

#define	CAN_F8R1_FB2 CAN_F8R1_FB2_Msk

#define	CAN_F8R1_FB3_Pos (3U)

#define	CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)

#define	CAN_F8R1_FB3 CAN_F8R1_FB3_Msk

#define	CAN_F8R1_FB4_Pos (4U)

#define	CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)

#define	CAN_F8R1_FB4 CAN_F8R1_FB4_Msk

#define	CAN_F8R1_FB5_Pos (5U)

#define	CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)

#define	CAN_F8R1_FB5 CAN_F8R1_FB5_Msk

#define	CAN_F8R1_FB6_Pos (6U)

#define	CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)

#define	CAN_F8R1_FB6 CAN_F8R1_FB6_Msk

#define	CAN_F8R1_FB7_Pos (7U)

#define	CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)

#define	CAN_F8R1_FB7 CAN_F8R1_FB7_Msk

#define	CAN_F8R1_FB8_Pos (8U)

#define	CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)

#define	CAN_F8R1_FB8 CAN_F8R1_FB8_Msk

#define	CAN_F8R1_FB9_Pos (9U)

#define	CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)

#define	CAN_F8R1_FB9 CAN_F8R1_FB9_Msk

#define	CAN_F8R1_FB10_Pos (10U)

#define	CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)

#define	CAN_F8R1_FB10 CAN_F8R1_FB10_Msk

#define	CAN_F8R1_FB11_Pos (11U)

#define	CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)

#define	CAN_F8R1_FB11 CAN_F8R1_FB11_Msk

#define	CAN_F8R1_FB12_Pos (12U)

#define	CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)

#define	CAN_F8R1_FB12 CAN_F8R1_FB12_Msk

#define	CAN_F8R1_FB13_Pos (13U)

#define	CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)

#define	CAN_F8R1_FB13 CAN_F8R1_FB13_Msk

#define	CAN_F8R1_FB14_Pos (14U)

#define	CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)

#define	CAN_F8R1_FB14 CAN_F8R1_FB14_Msk

#define	CAN_F8R1_FB15_Pos (15U)

#define	CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)

#define	CAN_F8R1_FB15 CAN_F8R1_FB15_Msk

#define	CAN_F8R1_FB16_Pos (16U)

#define	CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)

#define	CAN_F8R1_FB16 CAN_F8R1_FB16_Msk

#define	CAN_F8R1_FB17_Pos (17U)

#define	CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)

#define	CAN_F8R1_FB17 CAN_F8R1_FB17_Msk

#define	CAN_F8R1_FB18_Pos (18U)

#define	CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)

#define	CAN_F8R1_FB18 CAN_F8R1_FB18_Msk

#define	CAN_F8R1_FB19_Pos (19U)

#define	CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)

#define	CAN_F8R1_FB19 CAN_F8R1_FB19_Msk

#define	CAN_F8R1_FB20_Pos (20U)

#define	CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)

#define	CAN_F8R1_FB20 CAN_F8R1_FB20_Msk

#define	CAN_F8R1_FB21_Pos (21U)

#define	CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)

#define	CAN_F8R1_FB21 CAN_F8R1_FB21_Msk

#define	CAN_F8R1_FB22_Pos (22U)

#define	CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)

#define	CAN_F8R1_FB22 CAN_F8R1_FB22_Msk

#define	CAN_F8R1_FB23_Pos (23U)

#define	CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)

#define	CAN_F8R1_FB23 CAN_F8R1_FB23_Msk

#define	CAN_F8R1_FB24_Pos (24U)

#define	CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)

#define	CAN_F8R1_FB24 CAN_F8R1_FB24_Msk

#define	CAN_F8R1_FB25_Pos (25U)

#define	CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)

#define	CAN_F8R1_FB25 CAN_F8R1_FB25_Msk

#define	CAN_F8R1_FB26_Pos (26U)

#define	CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)

#define	CAN_F8R1_FB26 CAN_F8R1_FB26_Msk

#define	CAN_F8R1_FB27_Pos (27U)

#define	CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)

#define	CAN_F8R1_FB27 CAN_F8R1_FB27_Msk

#define	CAN_F8R1_FB28_Pos (28U)

#define	CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)

#define	CAN_F8R1_FB28 CAN_F8R1_FB28_Msk

#define	CAN_F8R1_FB29_Pos (29U)

#define	CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)

#define	CAN_F8R1_FB29 CAN_F8R1_FB29_Msk

#define	CAN_F8R1_FB30_Pos (30U)

#define	CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)

#define	CAN_F8R1_FB30 CAN_F8R1_FB30_Msk

#define	CAN_F8R1_FB31_Pos (31U)

#define	CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)

#define	CAN_F8R1_FB31 CAN_F8R1_FB31_Msk

#define	CAN_F9R1_FB0_Pos (0U)

#define	CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)

#define	CAN_F9R1_FB0 CAN_F9R1_FB0_Msk

#define	CAN_F9R1_FB1_Pos (1U)

#define	CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)

#define	CAN_F9R1_FB1 CAN_F9R1_FB1_Msk

#define	CAN_F9R1_FB2_Pos (2U)

#define	CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)

#define	CAN_F9R1_FB2 CAN_F9R1_FB2_Msk

#define	CAN_F9R1_FB3_Pos (3U)

#define	CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)

#define	CAN_F9R1_FB3 CAN_F9R1_FB3_Msk

#define	CAN_F9R1_FB4_Pos (4U)

#define	CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)

#define	CAN_F9R1_FB4 CAN_F9R1_FB4_Msk

#define	CAN_F9R1_FB5_Pos (5U)

#define	CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)

#define	CAN_F9R1_FB5 CAN_F9R1_FB5_Msk

#define	CAN_F9R1_FB6_Pos (6U)

#define	CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)

#define	CAN_F9R1_FB6 CAN_F9R1_FB6_Msk

#define	CAN_F9R1_FB7_Pos (7U)

#define	CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)

#define	CAN_F9R1_FB7 CAN_F9R1_FB7_Msk

#define	CAN_F9R1_FB8_Pos (8U)

#define	CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)

#define	CAN_F9R1_FB8 CAN_F9R1_FB8_Msk

#define	CAN_F9R1_FB9_Pos (9U)

#define	CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)

#define	CAN_F9R1_FB9 CAN_F9R1_FB9_Msk

#define	CAN_F9R1_FB10_Pos (10U)

#define	CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)

#define	CAN_F9R1_FB10 CAN_F9R1_FB10_Msk

#define	CAN_F9R1_FB11_Pos (11U)

#define	CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)

#define	CAN_F9R1_FB11 CAN_F9R1_FB11_Msk

#define	CAN_F9R1_FB12_Pos (12U)

#define	CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)

#define	CAN_F9R1_FB12 CAN_F9R1_FB12_Msk

#define	CAN_F9R1_FB13_Pos (13U)

#define	CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)

#define	CAN_F9R1_FB13 CAN_F9R1_FB13_Msk

#define	CAN_F9R1_FB14_Pos (14U)

#define	CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)

#define	CAN_F9R1_FB14 CAN_F9R1_FB14_Msk

#define	CAN_F9R1_FB15_Pos (15U)

#define	CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)

#define	CAN_F9R1_FB15 CAN_F9R1_FB15_Msk

#define	CAN_F9R1_FB16_Pos (16U)

#define	CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)

#define	CAN_F9R1_FB16 CAN_F9R1_FB16_Msk

#define	CAN_F9R1_FB17_Pos (17U)

#define	CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)

#define	CAN_F9R1_FB17 CAN_F9R1_FB17_Msk

#define	CAN_F9R1_FB18_Pos (18U)

#define	CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)

#define	CAN_F9R1_FB18 CAN_F9R1_FB18_Msk

#define	CAN_F9R1_FB19_Pos (19U)

#define	CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)

#define	CAN_F9R1_FB19 CAN_F9R1_FB19_Msk

#define	CAN_F9R1_FB20_Pos (20U)

#define	CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)

#define	CAN_F9R1_FB20 CAN_F9R1_FB20_Msk

#define	CAN_F9R1_FB21_Pos (21U)

#define	CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)

#define	CAN_F9R1_FB21 CAN_F9R1_FB21_Msk

#define	CAN_F9R1_FB22_Pos (22U)

#define	CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)

#define	CAN_F9R1_FB22 CAN_F9R1_FB22_Msk

#define	CAN_F9R1_FB23_Pos (23U)

#define	CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)

#define	CAN_F9R1_FB23 CAN_F9R1_FB23_Msk

#define	CAN_F9R1_FB24_Pos (24U)

#define	CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)

#define	CAN_F9R1_FB24 CAN_F9R1_FB24_Msk

#define	CAN_F9R1_FB25_Pos (25U)

#define	CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)

#define	CAN_F9R1_FB25 CAN_F9R1_FB25_Msk

#define	CAN_F9R1_FB26_Pos (26U)

#define	CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)

#define	CAN_F9R1_FB26 CAN_F9R1_FB26_Msk

#define	CAN_F9R1_FB27_Pos (27U)

#define	CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)

#define	CAN_F9R1_FB27 CAN_F9R1_FB27_Msk

#define	CAN_F9R1_FB28_Pos (28U)

#define	CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)

#define	CAN_F9R1_FB28 CAN_F9R1_FB28_Msk

#define	CAN_F9R1_FB29_Pos (29U)

#define	CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)

#define	CAN_F9R1_FB29 CAN_F9R1_FB29_Msk

#define	CAN_F9R1_FB30_Pos (30U)

#define	CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)

#define	CAN_F9R1_FB30 CAN_F9R1_FB30_Msk

#define	CAN_F9R1_FB31_Pos (31U)

#define	CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)

#define	CAN_F9R1_FB31 CAN_F9R1_FB31_Msk

#define	CAN_F10R1_FB0_Pos (0U)

#define	CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)

#define	CAN_F10R1_FB0 CAN_F10R1_FB0_Msk

#define	CAN_F10R1_FB1_Pos (1U)

#define	CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)

#define	CAN_F10R1_FB1 CAN_F10R1_FB1_Msk

#define	CAN_F10R1_FB2_Pos (2U)

#define	CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)

#define	CAN_F10R1_FB2 CAN_F10R1_FB2_Msk

#define	CAN_F10R1_FB3_Pos (3U)

#define	CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)

#define	CAN_F10R1_FB3 CAN_F10R1_FB3_Msk

#define	CAN_F10R1_FB4_Pos (4U)

#define	CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)

#define	CAN_F10R1_FB4 CAN_F10R1_FB4_Msk

#define	CAN_F10R1_FB5_Pos (5U)

#define	CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)

#define	CAN_F10R1_FB5 CAN_F10R1_FB5_Msk

#define	CAN_F10R1_FB6_Pos (6U)

#define	CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)

#define	CAN_F10R1_FB6 CAN_F10R1_FB6_Msk

#define	CAN_F10R1_FB7_Pos (7U)

#define	CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)

#define	CAN_F10R1_FB7 CAN_F10R1_FB7_Msk

#define	CAN_F10R1_FB8_Pos (8U)

#define	CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)

#define	CAN_F10R1_FB8 CAN_F10R1_FB8_Msk

#define	CAN_F10R1_FB9_Pos (9U)

#define	CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)

#define	CAN_F10R1_FB9 CAN_F10R1_FB9_Msk

#define	CAN_F10R1_FB10_Pos (10U)

#define	CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)

#define	CAN_F10R1_FB10 CAN_F10R1_FB10_Msk

#define	CAN_F10R1_FB11_Pos (11U)

#define	CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)

#define	CAN_F10R1_FB11 CAN_F10R1_FB11_Msk

#define	CAN_F10R1_FB12_Pos (12U)

#define	CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)

#define	CAN_F10R1_FB12 CAN_F10R1_FB12_Msk

#define	CAN_F10R1_FB13_Pos (13U)

#define	CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)

#define	CAN_F10R1_FB13 CAN_F10R1_FB13_Msk

#define	CAN_F10R1_FB14_Pos (14U)

#define	CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)

#define	CAN_F10R1_FB14 CAN_F10R1_FB14_Msk

#define	CAN_F10R1_FB15_Pos (15U)

#define	CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)

#define	CAN_F10R1_FB15 CAN_F10R1_FB15_Msk

#define	CAN_F10R1_FB16_Pos (16U)

#define	CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)

#define	CAN_F10R1_FB16 CAN_F10R1_FB16_Msk

#define	CAN_F10R1_FB17_Pos (17U)

#define	CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)

#define	CAN_F10R1_FB17 CAN_F10R1_FB17_Msk

#define	CAN_F10R1_FB18_Pos (18U)

#define	CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)

#define	CAN_F10R1_FB18 CAN_F10R1_FB18_Msk

#define	CAN_F10R1_FB19_Pos (19U)

#define	CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)

#define	CAN_F10R1_FB19 CAN_F10R1_FB19_Msk

#define	CAN_F10R1_FB20_Pos (20U)

#define	CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)

#define	CAN_F10R1_FB20 CAN_F10R1_FB20_Msk

#define	CAN_F10R1_FB21_Pos (21U)

#define	CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)

#define	CAN_F10R1_FB21 CAN_F10R1_FB21_Msk

#define	CAN_F10R1_FB22_Pos (22U)

#define	CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)

#define	CAN_F10R1_FB22 CAN_F10R1_FB22_Msk

#define	CAN_F10R1_FB23_Pos (23U)

#define	CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)

#define	CAN_F10R1_FB23 CAN_F10R1_FB23_Msk

#define	CAN_F10R1_FB24_Pos (24U)

#define	CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)

#define	CAN_F10R1_FB24 CAN_F10R1_FB24_Msk

#define	CAN_F10R1_FB25_Pos (25U)

#define	CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)

#define	CAN_F10R1_FB25 CAN_F10R1_FB25_Msk

#define	CAN_F10R1_FB26_Pos (26U)

#define	CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)

#define	CAN_F10R1_FB26 CAN_F10R1_FB26_Msk

#define	CAN_F10R1_FB27_Pos (27U)

#define	CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)

#define	CAN_F10R1_FB27 CAN_F10R1_FB27_Msk

#define	CAN_F10R1_FB28_Pos (28U)

#define	CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)

#define	CAN_F10R1_FB28 CAN_F10R1_FB28_Msk

#define	CAN_F10R1_FB29_Pos (29U)

#define	CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)

#define	CAN_F10R1_FB29 CAN_F10R1_FB29_Msk

#define	CAN_F10R1_FB30_Pos (30U)

#define	CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)

#define	CAN_F10R1_FB30 CAN_F10R1_FB30_Msk

#define	CAN_F10R1_FB31_Pos (31U)

#define	CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)

#define	CAN_F10R1_FB31 CAN_F10R1_FB31_Msk

#define	CAN_F11R1_FB0_Pos (0U)

#define	CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)

#define	CAN_F11R1_FB0 CAN_F11R1_FB0_Msk

#define	CAN_F11R1_FB1_Pos (1U)

#define	CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)

#define	CAN_F11R1_FB1 CAN_F11R1_FB1_Msk

#define	CAN_F11R1_FB2_Pos (2U)

#define	CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)

#define	CAN_F11R1_FB2 CAN_F11R1_FB2_Msk

#define	CAN_F11R1_FB3_Pos (3U)

#define	CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)

#define	CAN_F11R1_FB3 CAN_F11R1_FB3_Msk

#define	CAN_F11R1_FB4_Pos (4U)

#define	CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)

#define	CAN_F11R1_FB4 CAN_F11R1_FB4_Msk

#define	CAN_F11R1_FB5_Pos (5U)

#define	CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)

#define	CAN_F11R1_FB5 CAN_F11R1_FB5_Msk

#define	CAN_F11R1_FB6_Pos (6U)

#define	CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)

#define	CAN_F11R1_FB6 CAN_F11R1_FB6_Msk

#define	CAN_F11R1_FB7_Pos (7U)

#define	CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)

#define	CAN_F11R1_FB7 CAN_F11R1_FB7_Msk

#define	CAN_F11R1_FB8_Pos (8U)

#define	CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)

#define	CAN_F11R1_FB8 CAN_F11R1_FB8_Msk

#define	CAN_F11R1_FB9_Pos (9U)

#define	CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)

#define	CAN_F11R1_FB9 CAN_F11R1_FB9_Msk

#define	CAN_F11R1_FB10_Pos (10U)

#define	CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)

#define	CAN_F11R1_FB10 CAN_F11R1_FB10_Msk

#define	CAN_F11R1_FB11_Pos (11U)

#define	CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)

#define	CAN_F11R1_FB11 CAN_F11R1_FB11_Msk

#define	CAN_F11R1_FB12_Pos (12U)

#define	CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)

#define	CAN_F11R1_FB12 CAN_F11R1_FB12_Msk

#define	CAN_F11R1_FB13_Pos (13U)

#define	CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)

#define	CAN_F11R1_FB13 CAN_F11R1_FB13_Msk

#define	CAN_F11R1_FB14_Pos (14U)

#define	CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)

#define	CAN_F11R1_FB14 CAN_F11R1_FB14_Msk

#define	CAN_F11R1_FB15_Pos (15U)

#define	CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)

#define	CAN_F11R1_FB15 CAN_F11R1_FB15_Msk

#define	CAN_F11R1_FB16_Pos (16U)

#define	CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)

#define	CAN_F11R1_FB16 CAN_F11R1_FB16_Msk

#define	CAN_F11R1_FB17_Pos (17U)

#define	CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)

#define	CAN_F11R1_FB17 CAN_F11R1_FB17_Msk

#define	CAN_F11R1_FB18_Pos (18U)

#define	CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)

#define	CAN_F11R1_FB18 CAN_F11R1_FB18_Msk

#define	CAN_F11R1_FB19_Pos (19U)

#define	CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)

#define	CAN_F11R1_FB19 CAN_F11R1_FB19_Msk

#define	CAN_F11R1_FB20_Pos (20U)

#define	CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)

#define	CAN_F11R1_FB20 CAN_F11R1_FB20_Msk

#define	CAN_F11R1_FB21_Pos (21U)

#define	CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)

#define	CAN_F11R1_FB21 CAN_F11R1_FB21_Msk

#define	CAN_F11R1_FB22_Pos (22U)

#define	CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)

#define	CAN_F11R1_FB22 CAN_F11R1_FB22_Msk

#define	CAN_F11R1_FB23_Pos (23U)

#define	CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)

#define	CAN_F11R1_FB23 CAN_F11R1_FB23_Msk

#define	CAN_F11R1_FB24_Pos (24U)

#define	CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)

#define	CAN_F11R1_FB24 CAN_F11R1_FB24_Msk

#define	CAN_F11R1_FB25_Pos (25U)

#define	CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)

#define	CAN_F11R1_FB25 CAN_F11R1_FB25_Msk

#define	CAN_F11R1_FB26_Pos (26U)

#define	CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)

#define	CAN_F11R1_FB26 CAN_F11R1_FB26_Msk

#define	CAN_F11R1_FB27_Pos (27U)

#define	CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)

#define	CAN_F11R1_FB27 CAN_F11R1_FB27_Msk

#define	CAN_F11R1_FB28_Pos (28U)

#define	CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)

#define	CAN_F11R1_FB28 CAN_F11R1_FB28_Msk

#define	CAN_F11R1_FB29_Pos (29U)

#define	CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)

#define	CAN_F11R1_FB29 CAN_F11R1_FB29_Msk

#define	CAN_F11R1_FB30_Pos (30U)

#define	CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)

#define	CAN_F11R1_FB30 CAN_F11R1_FB30_Msk

#define	CAN_F11R1_FB31_Pos (31U)

#define	CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)

#define	CAN_F11R1_FB31 CAN_F11R1_FB31_Msk

#define	CAN_F12R1_FB0_Pos (0U)

#define	CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)

#define	CAN_F12R1_FB0 CAN_F12R1_FB0_Msk

#define	CAN_F12R1_FB1_Pos (1U)

#define	CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)

#define	CAN_F12R1_FB1 CAN_F12R1_FB1_Msk

#define	CAN_F12R1_FB2_Pos (2U)

#define	CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)

#define	CAN_F12R1_FB2 CAN_F12R1_FB2_Msk

#define	CAN_F12R1_FB3_Pos (3U)

#define	CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)

#define	CAN_F12R1_FB3 CAN_F12R1_FB3_Msk

#define	CAN_F12R1_FB4_Pos (4U)

#define	CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)

#define	CAN_F12R1_FB4 CAN_F12R1_FB4_Msk

#define	CAN_F12R1_FB5_Pos (5U)

#define	CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)

#define	CAN_F12R1_FB5 CAN_F12R1_FB5_Msk

#define	CAN_F12R1_FB6_Pos (6U)

#define	CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)

#define	CAN_F12R1_FB6 CAN_F12R1_FB6_Msk

#define	CAN_F12R1_FB7_Pos (7U)

#define	CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)

#define	CAN_F12R1_FB7 CAN_F12R1_FB7_Msk

#define	CAN_F12R1_FB8_Pos (8U)

#define	CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)

#define	CAN_F12R1_FB8 CAN_F12R1_FB8_Msk

#define	CAN_F12R1_FB9_Pos (9U)

#define	CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)

#define	CAN_F12R1_FB9 CAN_F12R1_FB9_Msk

#define	CAN_F12R1_FB10_Pos (10U)

#define	CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)

#define	CAN_F12R1_FB10 CAN_F12R1_FB10_Msk

#define	CAN_F12R1_FB11_Pos (11U)

#define	CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)

#define	CAN_F12R1_FB11 CAN_F12R1_FB11_Msk

#define	CAN_F12R1_FB12_Pos (12U)

#define	CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)

#define	CAN_F12R1_FB12 CAN_F12R1_FB12_Msk

#define	CAN_F12R1_FB13_Pos (13U)

#define	CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)

#define	CAN_F12R1_FB13 CAN_F12R1_FB13_Msk

#define	CAN_F12R1_FB14_Pos (14U)

#define	CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)

#define	CAN_F12R1_FB14 CAN_F12R1_FB14_Msk

#define	CAN_F12R1_FB15_Pos (15U)

#define	CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)

#define	CAN_F12R1_FB15 CAN_F12R1_FB15_Msk

#define	CAN_F12R1_FB16_Pos (16U)

#define	CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)

#define	CAN_F12R1_FB16 CAN_F12R1_FB16_Msk

#define	CAN_F12R1_FB17_Pos (17U)

#define	CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)

#define	CAN_F12R1_FB17 CAN_F12R1_FB17_Msk

#define	CAN_F12R1_FB18_Pos (18U)

#define	CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)

#define	CAN_F12R1_FB18 CAN_F12R1_FB18_Msk

#define	CAN_F12R1_FB19_Pos (19U)

#define	CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)

#define	CAN_F12R1_FB19 CAN_F12R1_FB19_Msk

#define	CAN_F12R1_FB20_Pos (20U)

#define	CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)

#define	CAN_F12R1_FB20 CAN_F12R1_FB20_Msk

#define	CAN_F12R1_FB21_Pos (21U)

#define	CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)

#define	CAN_F12R1_FB21 CAN_F12R1_FB21_Msk

#define	CAN_F12R1_FB22_Pos (22U)

#define	CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)

#define	CAN_F12R1_FB22 CAN_F12R1_FB22_Msk

#define	CAN_F12R1_FB23_Pos (23U)

#define	CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)

#define	CAN_F12R1_FB23 CAN_F12R1_FB23_Msk

#define	CAN_F12R1_FB24_Pos (24U)

#define	CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)

#define	CAN_F12R1_FB24 CAN_F12R1_FB24_Msk

#define	CAN_F12R1_FB25_Pos (25U)

#define	CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)

#define	CAN_F12R1_FB25 CAN_F12R1_FB25_Msk

#define	CAN_F12R1_FB26_Pos (26U)

#define	CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)

#define	CAN_F12R1_FB26 CAN_F12R1_FB26_Msk

#define	CAN_F12R1_FB27_Pos (27U)

#define	CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)

#define	CAN_F12R1_FB27 CAN_F12R1_FB27_Msk

#define	CAN_F12R1_FB28_Pos (28U)

#define	CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)

#define	CAN_F12R1_FB28 CAN_F12R1_FB28_Msk

#define	CAN_F12R1_FB29_Pos (29U)

#define	CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)

#define	CAN_F12R1_FB29 CAN_F12R1_FB29_Msk

#define	CAN_F12R1_FB30_Pos (30U)

#define	CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)

#define	CAN_F12R1_FB30 CAN_F12R1_FB30_Msk

#define	CAN_F12R1_FB31_Pos (31U)

#define	CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)

#define	CAN_F12R1_FB31 CAN_F12R1_FB31_Msk

#define	CAN_F13R1_FB0_Pos (0U)

#define	CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)

#define	CAN_F13R1_FB0 CAN_F13R1_FB0_Msk

#define	CAN_F13R1_FB1_Pos (1U)

#define	CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)

#define	CAN_F13R1_FB1 CAN_F13R1_FB1_Msk

#define	CAN_F13R1_FB2_Pos (2U)

#define	CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)

#define	CAN_F13R1_FB2 CAN_F13R1_FB2_Msk

#define	CAN_F13R1_FB3_Pos (3U)

#define	CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)

#define	CAN_F13R1_FB3 CAN_F13R1_FB3_Msk

#define	CAN_F13R1_FB4_Pos (4U)

#define	CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)

#define	CAN_F13R1_FB4 CAN_F13R1_FB4_Msk

#define	CAN_F13R1_FB5_Pos (5U)

#define	CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)

#define	CAN_F13R1_FB5 CAN_F13R1_FB5_Msk

#define	CAN_F13R1_FB6_Pos (6U)

#define	CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)

#define	CAN_F13R1_FB6 CAN_F13R1_FB6_Msk

#define	CAN_F13R1_FB7_Pos (7U)

#define	CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)

#define	CAN_F13R1_FB7 CAN_F13R1_FB7_Msk

#define	CAN_F13R1_FB8_Pos (8U)

#define	CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)

#define	CAN_F13R1_FB8 CAN_F13R1_FB8_Msk

#define	CAN_F13R1_FB9_Pos (9U)

#define	CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)

#define	CAN_F13R1_FB9 CAN_F13R1_FB9_Msk

#define	CAN_F13R1_FB10_Pos (10U)

#define	CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)

#define	CAN_F13R1_FB10 CAN_F13R1_FB10_Msk

#define	CAN_F13R1_FB11_Pos (11U)

#define	CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)

#define	CAN_F13R1_FB11 CAN_F13R1_FB11_Msk

#define	CAN_F13R1_FB12_Pos (12U)

#define	CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)

#define	CAN_F13R1_FB12 CAN_F13R1_FB12_Msk

#define	CAN_F13R1_FB13_Pos (13U)

#define	CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)

#define	CAN_F13R1_FB13 CAN_F13R1_FB13_Msk

#define	CAN_F13R1_FB14_Pos (14U)

#define	CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)

#define	CAN_F13R1_FB14 CAN_F13R1_FB14_Msk

#define	CAN_F13R1_FB15_Pos (15U)

#define	CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)

#define	CAN_F13R1_FB15 CAN_F13R1_FB15_Msk

#define	CAN_F13R1_FB16_Pos (16U)

#define	CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)

#define	CAN_F13R1_FB16 CAN_F13R1_FB16_Msk

#define	CAN_F13R1_FB17_Pos (17U)

#define	CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)

#define	CAN_F13R1_FB17 CAN_F13R1_FB17_Msk

#define	CAN_F13R1_FB18_Pos (18U)

#define	CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)

#define	CAN_F13R1_FB18 CAN_F13R1_FB18_Msk

#define	CAN_F13R1_FB19_Pos (19U)

#define	CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)

#define	CAN_F13R1_FB19 CAN_F13R1_FB19_Msk

#define	CAN_F13R1_FB20_Pos (20U)

#define	CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)

#define	CAN_F13R1_FB20 CAN_F13R1_FB20_Msk

#define	CAN_F13R1_FB21_Pos (21U)

#define	CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)

#define	CAN_F13R1_FB21 CAN_F13R1_FB21_Msk

#define	CAN_F13R1_FB22_Pos (22U)

#define	CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)

#define	CAN_F13R1_FB22 CAN_F13R1_FB22_Msk

#define	CAN_F13R1_FB23_Pos (23U)

#define	CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)

#define	CAN_F13R1_FB23 CAN_F13R1_FB23_Msk

#define	CAN_F13R1_FB24_Pos (24U)

#define	CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)

#define	CAN_F13R1_FB24 CAN_F13R1_FB24_Msk

#define	CAN_F13R1_FB25_Pos (25U)

#define	CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)

#define	CAN_F13R1_FB25 CAN_F13R1_FB25_Msk

#define	CAN_F13R1_FB26_Pos (26U)

#define	CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)

#define	CAN_F13R1_FB26 CAN_F13R1_FB26_Msk

#define	CAN_F13R1_FB27_Pos (27U)

#define	CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)

#define	CAN_F13R1_FB27 CAN_F13R1_FB27_Msk

#define	CAN_F13R1_FB28_Pos (28U)

#define	CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)

#define	CAN_F13R1_FB28 CAN_F13R1_FB28_Msk

#define	CAN_F13R1_FB29_Pos (29U)

#define	CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)

#define	CAN_F13R1_FB29 CAN_F13R1_FB29_Msk

#define	CAN_F13R1_FB30_Pos (30U)

#define	CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)

#define	CAN_F13R1_FB30 CAN_F13R1_FB30_Msk

#define	CAN_F13R1_FB31_Pos (31U)

#define	CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)

#define	CAN_F13R1_FB31 CAN_F13R1_FB31_Msk

#define	CAN_F0R2_FB0_Pos (0U)

#define	CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)

#define	CAN_F0R2_FB0 CAN_F0R2_FB0_Msk

#define	CAN_F0R2_FB1_Pos (1U)

#define	CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)

#define	CAN_F0R2_FB1 CAN_F0R2_FB1_Msk

#define	CAN_F0R2_FB2_Pos (2U)

#define	CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)

#define	CAN_F0R2_FB2 CAN_F0R2_FB2_Msk

#define	CAN_F0R2_FB3_Pos (3U)

#define	CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)

#define	CAN_F0R2_FB3 CAN_F0R2_FB3_Msk

#define	CAN_F0R2_FB4_Pos (4U)

#define	CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)

#define	CAN_F0R2_FB4 CAN_F0R2_FB4_Msk

#define	CAN_F0R2_FB5_Pos (5U)

#define	CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)

#define	CAN_F0R2_FB5 CAN_F0R2_FB5_Msk

#define	CAN_F0R2_FB6_Pos (6U)

#define	CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)

#define	CAN_F0R2_FB6 CAN_F0R2_FB6_Msk

#define	CAN_F0R2_FB7_Pos (7U)

#define	CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)

#define	CAN_F0R2_FB7 CAN_F0R2_FB7_Msk

#define	CAN_F0R2_FB8_Pos (8U)

#define	CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)

#define	CAN_F0R2_FB8 CAN_F0R2_FB8_Msk

#define	CAN_F0R2_FB9_Pos (9U)

#define	CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)

#define	CAN_F0R2_FB9 CAN_F0R2_FB9_Msk

#define	CAN_F0R2_FB10_Pos (10U)

#define	CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)

#define	CAN_F0R2_FB10 CAN_F0R2_FB10_Msk

#define	CAN_F0R2_FB11_Pos (11U)

#define	CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)

#define	CAN_F0R2_FB11 CAN_F0R2_FB11_Msk

#define	CAN_F0R2_FB12_Pos (12U)

#define	CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)

#define	CAN_F0R2_FB12 CAN_F0R2_FB12_Msk

#define	CAN_F0R2_FB13_Pos (13U)

#define	CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)

#define	CAN_F0R2_FB13 CAN_F0R2_FB13_Msk

#define	CAN_F0R2_FB14_Pos (14U)

#define	CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)

#define	CAN_F0R2_FB14 CAN_F0R2_FB14_Msk

#define	CAN_F0R2_FB15_Pos (15U)

#define	CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)

#define	CAN_F0R2_FB15 CAN_F0R2_FB15_Msk

#define	CAN_F0R2_FB16_Pos (16U)

#define	CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)

#define	CAN_F0R2_FB16 CAN_F0R2_FB16_Msk

#define	CAN_F0R2_FB17_Pos (17U)

#define	CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)

#define	CAN_F0R2_FB17 CAN_F0R2_FB17_Msk

#define	CAN_F0R2_FB18_Pos (18U)

#define	CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)

#define	CAN_F0R2_FB18 CAN_F0R2_FB18_Msk

#define	CAN_F0R2_FB19_Pos (19U)

#define	CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)

#define	CAN_F0R2_FB19 CAN_F0R2_FB19_Msk

#define	CAN_F0R2_FB20_Pos (20U)

#define	CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)

#define	CAN_F0R2_FB20 CAN_F0R2_FB20_Msk

#define	CAN_F0R2_FB21_Pos (21U)

#define	CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)

#define	CAN_F0R2_FB21 CAN_F0R2_FB21_Msk

#define	CAN_F0R2_FB22_Pos (22U)

#define	CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)

#define	CAN_F0R2_FB22 CAN_F0R2_FB22_Msk

#define	CAN_F0R2_FB23_Pos (23U)

#define	CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)

#define	CAN_F0R2_FB23 CAN_F0R2_FB23_Msk

#define	CAN_F0R2_FB24_Pos (24U)

#define	CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)

#define	CAN_F0R2_FB24 CAN_F0R2_FB24_Msk

#define	CAN_F0R2_FB25_Pos (25U)

#define	CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)

#define	CAN_F0R2_FB25 CAN_F0R2_FB25_Msk

#define	CAN_F0R2_FB26_Pos (26U)

#define	CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)

#define	CAN_F0R2_FB26 CAN_F0R2_FB26_Msk

#define	CAN_F0R2_FB27_Pos (27U)

#define	CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)

#define	CAN_F0R2_FB27 CAN_F0R2_FB27_Msk

#define	CAN_F0R2_FB28_Pos (28U)

#define	CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)

#define	CAN_F0R2_FB28 CAN_F0R2_FB28_Msk

#define	CAN_F0R2_FB29_Pos (29U)

#define	CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)

#define	CAN_F0R2_FB29 CAN_F0R2_FB29_Msk

#define	CAN_F0R2_FB30_Pos (30U)

#define	CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)

#define	CAN_F0R2_FB30 CAN_F0R2_FB30_Msk

#define	CAN_F0R2_FB31_Pos (31U)

#define	CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)

#define	CAN_F0R2_FB31 CAN_F0R2_FB31_Msk

#define	CAN_F1R2_FB0_Pos (0U)

#define	CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)

#define	CAN_F1R2_FB0 CAN_F1R2_FB0_Msk

#define	CAN_F1R2_FB1_Pos (1U)

#define	CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)

#define	CAN_F1R2_FB1 CAN_F1R2_FB1_Msk

#define	CAN_F1R2_FB2_Pos (2U)

#define	CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)

#define	CAN_F1R2_FB2 CAN_F1R2_FB2_Msk

#define	CAN_F1R2_FB3_Pos (3U)

#define	CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)

#define	CAN_F1R2_FB3 CAN_F1R2_FB3_Msk

#define	CAN_F1R2_FB4_Pos (4U)

#define	CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)

#define	CAN_F1R2_FB4 CAN_F1R2_FB4_Msk

#define	CAN_F1R2_FB5_Pos (5U)

#define	CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)

#define	CAN_F1R2_FB5 CAN_F1R2_FB5_Msk

#define	CAN_F1R2_FB6_Pos (6U)

#define	CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)

#define	CAN_F1R2_FB6 CAN_F1R2_FB6_Msk

#define	CAN_F1R2_FB7_Pos (7U)

#define	CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)

#define	CAN_F1R2_FB7 CAN_F1R2_FB7_Msk

#define	CAN_F1R2_FB8_Pos (8U)

#define	CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)

#define	CAN_F1R2_FB8 CAN_F1R2_FB8_Msk

#define	CAN_F1R2_FB9_Pos (9U)

#define	CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)

#define	CAN_F1R2_FB9 CAN_F1R2_FB9_Msk

#define	CAN_F1R2_FB10_Pos (10U)

#define	CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)

#define	CAN_F1R2_FB10 CAN_F1R2_FB10_Msk

#define	CAN_F1R2_FB11_Pos (11U)

#define	CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)

#define	CAN_F1R2_FB11 CAN_F1R2_FB11_Msk

#define	CAN_F1R2_FB12_Pos (12U)

#define	CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)

#define	CAN_F1R2_FB12 CAN_F1R2_FB12_Msk

#define	CAN_F1R2_FB13_Pos (13U)

#define	CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)

#define	CAN_F1R2_FB13 CAN_F1R2_FB13_Msk

#define	CAN_F1R2_FB14_Pos (14U)

#define	CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)

#define	CAN_F1R2_FB14 CAN_F1R2_FB14_Msk

#define	CAN_F1R2_FB15_Pos (15U)

#define	CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)

#define	CAN_F1R2_FB15 CAN_F1R2_FB15_Msk

#define	CAN_F1R2_FB16_Pos (16U)

#define	CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)

#define	CAN_F1R2_FB16 CAN_F1R2_FB16_Msk

#define	CAN_F1R2_FB17_Pos (17U)

#define	CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)

#define	CAN_F1R2_FB17 CAN_F1R2_FB17_Msk

#define	CAN_F1R2_FB18_Pos (18U)

#define	CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)

#define	CAN_F1R2_FB18 CAN_F1R2_FB18_Msk

#define	CAN_F1R2_FB19_Pos (19U)

#define	CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)

#define	CAN_F1R2_FB19 CAN_F1R2_FB19_Msk

#define	CAN_F1R2_FB20_Pos (20U)

#define	CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)

#define	CAN_F1R2_FB20 CAN_F1R2_FB20_Msk

#define	CAN_F1R2_FB21_Pos (21U)

#define	CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)

#define	CAN_F1R2_FB21 CAN_F1R2_FB21_Msk

#define	CAN_F1R2_FB22_Pos (22U)

#define	CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)

#define	CAN_F1R2_FB22 CAN_F1R2_FB22_Msk

#define	CAN_F1R2_FB23_Pos (23U)

#define	CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)

#define	CAN_F1R2_FB23 CAN_F1R2_FB23_Msk

#define	CAN_F1R2_FB24_Pos (24U)

#define	CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)

#define	CAN_F1R2_FB24 CAN_F1R2_FB24_Msk

#define	CAN_F1R2_FB25_Pos (25U)

#define	CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)

#define	CAN_F1R2_FB25 CAN_F1R2_FB25_Msk

#define	CAN_F1R2_FB26_Pos (26U)

#define	CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)

#define	CAN_F1R2_FB26 CAN_F1R2_FB26_Msk

#define	CAN_F1R2_FB27_Pos (27U)

#define	CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)

#define	CAN_F1R2_FB27 CAN_F1R2_FB27_Msk

#define	CAN_F1R2_FB28_Pos (28U)

#define	CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)

#define	CAN_F1R2_FB28 CAN_F1R2_FB28_Msk

#define	CAN_F1R2_FB29_Pos (29U)

#define	CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)

#define	CAN_F1R2_FB29 CAN_F1R2_FB29_Msk

#define	CAN_F1R2_FB30_Pos (30U)

#define	CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)

#define	CAN_F1R2_FB30 CAN_F1R2_FB30_Msk

#define	CAN_F1R2_FB31_Pos (31U)

#define	CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)

#define	CAN_F1R2_FB31 CAN_F1R2_FB31_Msk

#define	CAN_F2R2_FB0_Pos (0U)

#define	CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)

#define	CAN_F2R2_FB0 CAN_F2R2_FB0_Msk

#define	CAN_F2R2_FB1_Pos (1U)

#define	CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)

#define	CAN_F2R2_FB1 CAN_F2R2_FB1_Msk

#define	CAN_F2R2_FB2_Pos (2U)

#define	CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)

#define	CAN_F2R2_FB2 CAN_F2R2_FB2_Msk

#define	CAN_F2R2_FB3_Pos (3U)

#define	CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)

#define	CAN_F2R2_FB3 CAN_F2R2_FB3_Msk

#define	CAN_F2R2_FB4_Pos (4U)

#define	CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)

#define	CAN_F2R2_FB4 CAN_F2R2_FB4_Msk

#define	CAN_F2R2_FB5_Pos (5U)

#define	CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)

#define	CAN_F2R2_FB5 CAN_F2R2_FB5_Msk

#define	CAN_F2R2_FB6_Pos (6U)

#define	CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)

#define	CAN_F2R2_FB6 CAN_F2R2_FB6_Msk

#define	CAN_F2R2_FB7_Pos (7U)

#define	CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)

#define	CAN_F2R2_FB7 CAN_F2R2_FB7_Msk

#define	CAN_F2R2_FB8_Pos (8U)

#define	CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)

#define	CAN_F2R2_FB8 CAN_F2R2_FB8_Msk

#define	CAN_F2R2_FB9_Pos (9U)

#define	CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)

#define	CAN_F2R2_FB9 CAN_F2R2_FB9_Msk

#define	CAN_F2R2_FB10_Pos (10U)

#define	CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)

#define	CAN_F2R2_FB10 CAN_F2R2_FB10_Msk

#define	CAN_F2R2_FB11_Pos (11U)

#define	CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)

#define	CAN_F2R2_FB11 CAN_F2R2_FB11_Msk

#define	CAN_F2R2_FB12_Pos (12U)

#define	CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)

#define	CAN_F2R2_FB12 CAN_F2R2_FB12_Msk

#define	CAN_F2R2_FB13_Pos (13U)

#define	CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)

#define	CAN_F2R2_FB13 CAN_F2R2_FB13_Msk

#define	CAN_F2R2_FB14_Pos (14U)

#define	CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)

#define	CAN_F2R2_FB14 CAN_F2R2_FB14_Msk

#define	CAN_F2R2_FB15_Pos (15U)

#define	CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)

#define	CAN_F2R2_FB15 CAN_F2R2_FB15_Msk

#define	CAN_F2R2_FB16_Pos (16U)

#define	CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)

#define	CAN_F2R2_FB16 CAN_F2R2_FB16_Msk

#define	CAN_F2R2_FB17_Pos (17U)

#define	CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)

#define	CAN_F2R2_FB17 CAN_F2R2_FB17_Msk

#define	CAN_F2R2_FB18_Pos (18U)

#define	CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)

#define	CAN_F2R2_FB18 CAN_F2R2_FB18_Msk

#define	CAN_F2R2_FB19_Pos (19U)

#define	CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)

#define	CAN_F2R2_FB19 CAN_F2R2_FB19_Msk

#define	CAN_F2R2_FB20_Pos (20U)

#define	CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)

#define	CAN_F2R2_FB20 CAN_F2R2_FB20_Msk

#define	CAN_F2R2_FB21_Pos (21U)

#define	CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)

#define	CAN_F2R2_FB21 CAN_F2R2_FB21_Msk

#define	CAN_F2R2_FB22_Pos (22U)

#define	CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)

#define	CAN_F2R2_FB22 CAN_F2R2_FB22_Msk

#define	CAN_F2R2_FB23_Pos (23U)

#define	CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)

#define	CAN_F2R2_FB23 CAN_F2R2_FB23_Msk

#define	CAN_F2R2_FB24_Pos (24U)

#define	CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)

#define	CAN_F2R2_FB24 CAN_F2R2_FB24_Msk

#define	CAN_F2R2_FB25_Pos (25U)

#define	CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)

#define	CAN_F2R2_FB25 CAN_F2R2_FB25_Msk

#define	CAN_F2R2_FB26_Pos (26U)

#define	CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)

#define	CAN_F2R2_FB26 CAN_F2R2_FB26_Msk

#define	CAN_F2R2_FB27_Pos (27U)

#define	CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)

#define	CAN_F2R2_FB27 CAN_F2R2_FB27_Msk

#define	CAN_F2R2_FB28_Pos (28U)

#define	CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)

#define	CAN_F2R2_FB28 CAN_F2R2_FB28_Msk

#define	CAN_F2R2_FB29_Pos (29U)

#define	CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)

#define	CAN_F2R2_FB29 CAN_F2R2_FB29_Msk

#define	CAN_F2R2_FB30_Pos (30U)

#define	CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)

#define	CAN_F2R2_FB30 CAN_F2R2_FB30_Msk

#define	CAN_F2R2_FB31_Pos (31U)

#define	CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)

#define	CAN_F2R2_FB31 CAN_F2R2_FB31_Msk

#define	CAN_F3R2_FB0_Pos (0U)

#define	CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)

#define	CAN_F3R2_FB0 CAN_F3R2_FB0_Msk

#define	CAN_F3R2_FB1_Pos (1U)

#define	CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)

#define	CAN_F3R2_FB1 CAN_F3R2_FB1_Msk

#define	CAN_F3R2_FB2_Pos (2U)

#define	CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)

#define	CAN_F3R2_FB2 CAN_F3R2_FB2_Msk

#define	CAN_F3R2_FB3_Pos (3U)

#define	CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)

#define	CAN_F3R2_FB3 CAN_F3R2_FB3_Msk

#define	CAN_F3R2_FB4_Pos (4U)

#define	CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)

#define	CAN_F3R2_FB4 CAN_F3R2_FB4_Msk

#define	CAN_F3R2_FB5_Pos (5U)

#define	CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)

#define	CAN_F3R2_FB5 CAN_F3R2_FB5_Msk

#define	CAN_F3R2_FB6_Pos (6U)

#define	CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)

#define	CAN_F3R2_FB6 CAN_F3R2_FB6_Msk

#define	CAN_F3R2_FB7_Pos (7U)

#define	CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)

#define	CAN_F3R2_FB7 CAN_F3R2_FB7_Msk

#define	CAN_F3R2_FB8_Pos (8U)

#define	CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)

#define	CAN_F3R2_FB8 CAN_F3R2_FB8_Msk

#define	CAN_F3R2_FB9_Pos (9U)

#define	CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)

#define	CAN_F3R2_FB9 CAN_F3R2_FB9_Msk

#define	CAN_F3R2_FB10_Pos (10U)

#define	CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)

#define	CAN_F3R2_FB10 CAN_F3R2_FB10_Msk

#define	CAN_F3R2_FB11_Pos (11U)

#define	CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)

#define	CAN_F3R2_FB11 CAN_F3R2_FB11_Msk

#define	CAN_F3R2_FB12_Pos (12U)

#define	CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)

#define	CAN_F3R2_FB12 CAN_F3R2_FB12_Msk

#define	CAN_F3R2_FB13_Pos (13U)

#define	CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)

#define	CAN_F3R2_FB13 CAN_F3R2_FB13_Msk

#define	CAN_F3R2_FB14_Pos (14U)

#define	CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)

#define	CAN_F3R2_FB14 CAN_F3R2_FB14_Msk

#define	CAN_F3R2_FB15_Pos (15U)

#define	CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)

#define	CAN_F3R2_FB15 CAN_F3R2_FB15_Msk

#define	CAN_F3R2_FB16_Pos (16U)

#define	CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)

#define	CAN_F3R2_FB16 CAN_F3R2_FB16_Msk

#define	CAN_F3R2_FB17_Pos (17U)

#define	CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)

#define	CAN_F3R2_FB17 CAN_F3R2_FB17_Msk

#define	CAN_F3R2_FB18_Pos (18U)

#define	CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)

#define	CAN_F3R2_FB18 CAN_F3R2_FB18_Msk

#define	CAN_F3R2_FB19_Pos (19U)

#define	CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)

#define	CAN_F3R2_FB19 CAN_F3R2_FB19_Msk

#define	CAN_F3R2_FB20_Pos (20U)

#define	CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)

#define	CAN_F3R2_FB20 CAN_F3R2_FB20_Msk

#define	CAN_F3R2_FB21_Pos (21U)

#define	CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)

#define	CAN_F3R2_FB21 CAN_F3R2_FB21_Msk

#define	CAN_F3R2_FB22_Pos (22U)

#define	CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)

#define	CAN_F3R2_FB22 CAN_F3R2_FB22_Msk

#define	CAN_F3R2_FB23_Pos (23U)

#define	CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)

#define	CAN_F3R2_FB23 CAN_F3R2_FB23_Msk

#define	CAN_F3R2_FB24_Pos (24U)

#define	CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)

#define	CAN_F3R2_FB24 CAN_F3R2_FB24_Msk

#define	CAN_F3R2_FB25_Pos (25U)

#define	CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)

#define	CAN_F3R2_FB25 CAN_F3R2_FB25_Msk

#define	CAN_F3R2_FB26_Pos (26U)

#define	CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)

#define	CAN_F3R2_FB26 CAN_F3R2_FB26_Msk

#define	CAN_F3R2_FB27_Pos (27U)

#define	CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)

#define	CAN_F3R2_FB27 CAN_F3R2_FB27_Msk

#define	CAN_F3R2_FB28_Pos (28U)

#define	CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)

#define	CAN_F3R2_FB28 CAN_F3R2_FB28_Msk

#define	CAN_F3R2_FB29_Pos (29U)

#define	CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)

#define	CAN_F3R2_FB29 CAN_F3R2_FB29_Msk

#define	CAN_F3R2_FB30_Pos (30U)

#define	CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)

#define	CAN_F3R2_FB30 CAN_F3R2_FB30_Msk

#define	CAN_F3R2_FB31_Pos (31U)

#define	CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)

#define	CAN_F3R2_FB31 CAN_F3R2_FB31_Msk

#define	CAN_F4R2_FB0_Pos (0U)

#define	CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)

#define	CAN_F4R2_FB0 CAN_F4R2_FB0_Msk

#define	CAN_F4R2_FB1_Pos (1U)

#define	CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)

#define	CAN_F4R2_FB1 CAN_F4R2_FB1_Msk

#define	CAN_F4R2_FB2_Pos (2U)

#define	CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)

#define	CAN_F4R2_FB2 CAN_F4R2_FB2_Msk

#define	CAN_F4R2_FB3_Pos (3U)

#define	CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)

#define	CAN_F4R2_FB3 CAN_F4R2_FB3_Msk

#define	CAN_F4R2_FB4_Pos (4U)

#define	CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)

#define	CAN_F4R2_FB4 CAN_F4R2_FB4_Msk

#define	CAN_F4R2_FB5_Pos (5U)

#define	CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)

#define	CAN_F4R2_FB5 CAN_F4R2_FB5_Msk

#define	CAN_F4R2_FB6_Pos (6U)

#define	CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)

#define	CAN_F4R2_FB6 CAN_F4R2_FB6_Msk

#define	CAN_F4R2_FB7_Pos (7U)

#define	CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)

#define	CAN_F4R2_FB7 CAN_F4R2_FB7_Msk

#define	CAN_F4R2_FB8_Pos (8U)

#define	CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)

#define	CAN_F4R2_FB8 CAN_F4R2_FB8_Msk

#define	CAN_F4R2_FB9_Pos (9U)

#define	CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)

#define	CAN_F4R2_FB9 CAN_F4R2_FB9_Msk

#define	CAN_F4R2_FB10_Pos (10U)

#define	CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)

#define	CAN_F4R2_FB10 CAN_F4R2_FB10_Msk

#define	CAN_F4R2_FB11_Pos (11U)

#define	CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)

#define	CAN_F4R2_FB11 CAN_F4R2_FB11_Msk

#define	CAN_F4R2_FB12_Pos (12U)

#define	CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)

#define	CAN_F4R2_FB12 CAN_F4R2_FB12_Msk

#define	CAN_F4R2_FB13_Pos (13U)

#define	CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)

#define	CAN_F4R2_FB13 CAN_F4R2_FB13_Msk

#define	CAN_F4R2_FB14_Pos (14U)

#define	CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)

#define	CAN_F4R2_FB14 CAN_F4R2_FB14_Msk

#define	CAN_F4R2_FB15_Pos (15U)

#define	CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)

#define	CAN_F4R2_FB15 CAN_F4R2_FB15_Msk

#define	CAN_F4R2_FB16_Pos (16U)

#define	CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)

#define	CAN_F4R2_FB16 CAN_F4R2_FB16_Msk

#define	CAN_F4R2_FB17_Pos (17U)

#define	CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)

#define	CAN_F4R2_FB17 CAN_F4R2_FB17_Msk

#define	CAN_F4R2_FB18_Pos (18U)

#define	CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)

#define	CAN_F4R2_FB18 CAN_F4R2_FB18_Msk

#define	CAN_F4R2_FB19_Pos (19U)

#define	CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)

#define	CAN_F4R2_FB19 CAN_F4R2_FB19_Msk

#define	CAN_F4R2_FB20_Pos (20U)

#define	CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)

#define	CAN_F4R2_FB20 CAN_F4R2_FB20_Msk

#define	CAN_F4R2_FB21_Pos (21U)

#define	CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)

#define	CAN_F4R2_FB21 CAN_F4R2_FB21_Msk

#define	CAN_F4R2_FB22_Pos (22U)

#define	CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)

#define	CAN_F4R2_FB22 CAN_F4R2_FB22_Msk

#define	CAN_F4R2_FB23_Pos (23U)

#define	CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)

#define	CAN_F4R2_FB23 CAN_F4R2_FB23_Msk

#define	CAN_F4R2_FB24_Pos (24U)

#define	CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)

#define	CAN_F4R2_FB24 CAN_F4R2_FB24_Msk

#define	CAN_F4R2_FB25_Pos (25U)

#define	CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)

#define	CAN_F4R2_FB25 CAN_F4R2_FB25_Msk

#define	CAN_F4R2_FB26_Pos (26U)

#define	CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)

#define	CAN_F4R2_FB26 CAN_F4R2_FB26_Msk

#define	CAN_F4R2_FB27_Pos (27U)

#define	CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)

#define	CAN_F4R2_FB27 CAN_F4R2_FB27_Msk

#define	CAN_F4R2_FB28_Pos (28U)

#define	CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)

#define	CAN_F4R2_FB28 CAN_F4R2_FB28_Msk

#define	CAN_F4R2_FB29_Pos (29U)

#define	CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)

#define	CAN_F4R2_FB29 CAN_F4R2_FB29_Msk

#define	CAN_F4R2_FB30_Pos (30U)

#define	CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)

#define	CAN_F4R2_FB30 CAN_F4R2_FB30_Msk

#define	CAN_F4R2_FB31_Pos (31U)

#define	CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)

#define	CAN_F4R2_FB31 CAN_F4R2_FB31_Msk

#define	CAN_F5R2_FB0_Pos (0U)

#define	CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)

#define	CAN_F5R2_FB0 CAN_F5R2_FB0_Msk

#define	CAN_F5R2_FB1_Pos (1U)

#define	CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)

#define	CAN_F5R2_FB1 CAN_F5R2_FB1_Msk

#define	CAN_F5R2_FB2_Pos (2U)

#define	CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)

#define	CAN_F5R2_FB2 CAN_F5R2_FB2_Msk

#define	CAN_F5R2_FB3_Pos (3U)

#define	CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)

#define	CAN_F5R2_FB3 CAN_F5R2_FB3_Msk

#define	CAN_F5R2_FB4_Pos (4U)

#define	CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)

#define	CAN_F5R2_FB4 CAN_F5R2_FB4_Msk

#define	CAN_F5R2_FB5_Pos (5U)

#define	CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)

#define	CAN_F5R2_FB5 CAN_F5R2_FB5_Msk

#define	CAN_F5R2_FB6_Pos (6U)

#define	CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)

#define	CAN_F5R2_FB6 CAN_F5R2_FB6_Msk

#define	CAN_F5R2_FB7_Pos (7U)

#define	CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)

#define	CAN_F5R2_FB7 CAN_F5R2_FB7_Msk

#define	CAN_F5R2_FB8_Pos (8U)

#define	CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)

#define	CAN_F5R2_FB8 CAN_F5R2_FB8_Msk

#define	CAN_F5R2_FB9_Pos (9U)

#define	CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)

#define	CAN_F5R2_FB9 CAN_F5R2_FB9_Msk

#define	CAN_F5R2_FB10_Pos (10U)

#define	CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)

#define	CAN_F5R2_FB10 CAN_F5R2_FB10_Msk

#define	CAN_F5R2_FB11_Pos (11U)

#define	CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)

#define	CAN_F5R2_FB11 CAN_F5R2_FB11_Msk

#define	CAN_F5R2_FB12_Pos (12U)

#define	CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)

#define	CAN_F5R2_FB12 CAN_F5R2_FB12_Msk

#define	CAN_F5R2_FB13_Pos (13U)

#define	CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)

#define	CAN_F5R2_FB13 CAN_F5R2_FB13_Msk

#define	CAN_F5R2_FB14_Pos (14U)

#define	CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)

#define	CAN_F5R2_FB14 CAN_F5R2_FB14_Msk

#define	CAN_F5R2_FB15_Pos (15U)

#define	CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)

#define	CAN_F5R2_FB15 CAN_F5R2_FB15_Msk

#define	CAN_F5R2_FB16_Pos (16U)

#define	CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)

#define	CAN_F5R2_FB16 CAN_F5R2_FB16_Msk

#define	CAN_F5R2_FB17_Pos (17U)

#define	CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)

#define	CAN_F5R2_FB17 CAN_F5R2_FB17_Msk

#define	CAN_F5R2_FB18_Pos (18U)

#define	CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)

#define	CAN_F5R2_FB18 CAN_F5R2_FB18_Msk

#define	CAN_F5R2_FB19_Pos (19U)

#define	CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)

#define	CAN_F5R2_FB19 CAN_F5R2_FB19_Msk

#define	CAN_F5R2_FB20_Pos (20U)

#define	CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)

#define	CAN_F5R2_FB20 CAN_F5R2_FB20_Msk

#define	CAN_F5R2_FB21_Pos (21U)

#define	CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)

#define	CAN_F5R2_FB21 CAN_F5R2_FB21_Msk

#define	CAN_F5R2_FB22_Pos (22U)

#define	CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)

#define	CAN_F5R2_FB22 CAN_F5R2_FB22_Msk

#define	CAN_F5R2_FB23_Pos (23U)

#define	CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)

#define	CAN_F5R2_FB23 CAN_F5R2_FB23_Msk

#define	CAN_F5R2_FB24_Pos (24U)

#define	CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)

#define	CAN_F5R2_FB24 CAN_F5R2_FB24_Msk

#define	CAN_F5R2_FB25_Pos (25U)

#define	CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)

#define	CAN_F5R2_FB25 CAN_F5R2_FB25_Msk

#define	CAN_F5R2_FB26_Pos (26U)

#define	CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)

#define	CAN_F5R2_FB26 CAN_F5R2_FB26_Msk

#define	CAN_F5R2_FB27_Pos (27U)

#define	CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)

#define	CAN_F5R2_FB27 CAN_F5R2_FB27_Msk

#define	CAN_F5R2_FB28_Pos (28U)

#define	CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)

#define	CAN_F5R2_FB28 CAN_F5R2_FB28_Msk

#define	CAN_F5R2_FB29_Pos (29U)

#define	CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)

#define	CAN_F5R2_FB29 CAN_F5R2_FB29_Msk

#define	CAN_F5R2_FB30_Pos (30U)

#define	CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)

#define	CAN_F5R2_FB30 CAN_F5R2_FB30_Msk

#define	CAN_F5R2_FB31_Pos (31U)

#define	CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)

#define	CAN_F5R2_FB31 CAN_F5R2_FB31_Msk

#define	CAN_F6R2_FB0_Pos (0U)

#define	CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)

#define	CAN_F6R2_FB0 CAN_F6R2_FB0_Msk

#define	CAN_F6R2_FB1_Pos (1U)

#define	CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)

#define	CAN_F6R2_FB1 CAN_F6R2_FB1_Msk

#define	CAN_F6R2_FB2_Pos (2U)

#define	CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)

#define	CAN_F6R2_FB2 CAN_F6R2_FB2_Msk

#define	CAN_F6R2_FB3_Pos (3U)

#define	CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)

#define	CAN_F6R2_FB3 CAN_F6R2_FB3_Msk

#define	CAN_F6R2_FB4_Pos (4U)

#define	CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)

#define	CAN_F6R2_FB4 CAN_F6R2_FB4_Msk

#define	CAN_F6R2_FB5_Pos (5U)

#define	CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)

#define	CAN_F6R2_FB5 CAN_F6R2_FB5_Msk

#define	CAN_F6R2_FB6_Pos (6U)

#define	CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)

#define	CAN_F6R2_FB6 CAN_F6R2_FB6_Msk

#define	CAN_F6R2_FB7_Pos (7U)

#define	CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)

#define	CAN_F6R2_FB7 CAN_F6R2_FB7_Msk

#define	CAN_F6R2_FB8_Pos (8U)

#define	CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)

#define	CAN_F6R2_FB8 CAN_F6R2_FB8_Msk

#define	CAN_F6R2_FB9_Pos (9U)

#define	CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)

#define	CAN_F6R2_FB9 CAN_F6R2_FB9_Msk

#define	CAN_F6R2_FB10_Pos (10U)

#define	CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)

#define	CAN_F6R2_FB10 CAN_F6R2_FB10_Msk

#define	CAN_F6R2_FB11_Pos (11U)

#define	CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)

#define	CAN_F6R2_FB11 CAN_F6R2_FB11_Msk

#define	CAN_F6R2_FB12_Pos (12U)

#define	CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)

#define	CAN_F6R2_FB12 CAN_F6R2_FB12_Msk

#define	CAN_F6R2_FB13_Pos (13U)

#define	CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)

#define	CAN_F6R2_FB13 CAN_F6R2_FB13_Msk

#define	CAN_F6R2_FB14_Pos (14U)

#define	CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)

#define	CAN_F6R2_FB14 CAN_F6R2_FB14_Msk

#define	CAN_F6R2_FB15_Pos (15U)

#define	CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)

#define	CAN_F6R2_FB15 CAN_F6R2_FB15_Msk

#define	CAN_F6R2_FB16_Pos (16U)

#define	CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)

#define	CAN_F6R2_FB16 CAN_F6R2_FB16_Msk

#define	CAN_F6R2_FB17_Pos (17U)

#define	CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)

#define	CAN_F6R2_FB17 CAN_F6R2_FB17_Msk

#define	CAN_F6R2_FB18_Pos (18U)

#define	CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)

#define	CAN_F6R2_FB18 CAN_F6R2_FB18_Msk

#define	CAN_F6R2_FB19_Pos (19U)

#define	CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)

#define	CAN_F6R2_FB19 CAN_F6R2_FB19_Msk

#define	CAN_F6R2_FB20_Pos (20U)

#define	CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)

#define	CAN_F6R2_FB20 CAN_F6R2_FB20_Msk

#define	CAN_F6R2_FB21_Pos (21U)

#define	CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)

#define	CAN_F6R2_FB21 CAN_F6R2_FB21_Msk

#define	CAN_F6R2_FB22_Pos (22U)

#define	CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)

#define	CAN_F6R2_FB22 CAN_F6R2_FB22_Msk

#define	CAN_F6R2_FB23_Pos (23U)

#define	CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)

#define	CAN_F6R2_FB23 CAN_F6R2_FB23_Msk

#define	CAN_F6R2_FB24_Pos (24U)

#define	CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)

#define	CAN_F6R2_FB24 CAN_F6R2_FB24_Msk

#define	CAN_F6R2_FB25_Pos (25U)

#define	CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)

#define	CAN_F6R2_FB25 CAN_F6R2_FB25_Msk

#define	CAN_F6R2_FB26_Pos (26U)

#define	CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)

#define	CAN_F6R2_FB26 CAN_F6R2_FB26_Msk

#define	CAN_F6R2_FB27_Pos (27U)

#define	CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)

#define	CAN_F6R2_FB27 CAN_F6R2_FB27_Msk

#define	CAN_F6R2_FB28_Pos (28U)

#define	CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)

#define	CAN_F6R2_FB28 CAN_F6R2_FB28_Msk

#define	CAN_F6R2_FB29_Pos (29U)

#define	CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)

#define	CAN_F6R2_FB29 CAN_F6R2_FB29_Msk

#define	CAN_F6R2_FB30_Pos (30U)

#define	CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)

#define	CAN_F6R2_FB30 CAN_F6R2_FB30_Msk

#define	CAN_F6R2_FB31_Pos (31U)

#define	CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)

#define	CAN_F6R2_FB31 CAN_F6R2_FB31_Msk

#define	CAN_F7R2_FB0_Pos (0U)

#define	CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)

#define	CAN_F7R2_FB0 CAN_F7R2_FB0_Msk

#define	CAN_F7R2_FB1_Pos (1U)

#define	CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)

#define	CAN_F7R2_FB1 CAN_F7R2_FB1_Msk

#define	CAN_F7R2_FB2_Pos (2U)

#define	CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)

#define	CAN_F7R2_FB2 CAN_F7R2_FB2_Msk

#define	CAN_F7R2_FB3_Pos (3U)

#define	CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)

#define	CAN_F7R2_FB3 CAN_F7R2_FB3_Msk

#define	CAN_F7R2_FB4_Pos (4U)

#define	CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)

#define	CAN_F7R2_FB4 CAN_F7R2_FB4_Msk

#define	CAN_F7R2_FB5_Pos (5U)

#define	CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)

#define	CAN_F7R2_FB5 CAN_F7R2_FB5_Msk

#define	CAN_F7R2_FB6_Pos (6U)

#define	CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)

#define	CAN_F7R2_FB6 CAN_F7R2_FB6_Msk

#define	CAN_F7R2_FB7_Pos (7U)

#define	CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)

#define	CAN_F7R2_FB7 CAN_F7R2_FB7_Msk

#define	CAN_F7R2_FB8_Pos (8U)

#define	CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)

#define	CAN_F7R2_FB8 CAN_F7R2_FB8_Msk

#define	CAN_F7R2_FB9_Pos (9U)

#define	CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)

#define	CAN_F7R2_FB9 CAN_F7R2_FB9_Msk

#define	CAN_F7R2_FB10_Pos (10U)

#define	CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)

#define	CAN_F7R2_FB10 CAN_F7R2_FB10_Msk

#define	CAN_F7R2_FB11_Pos (11U)

#define	CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)

#define	CAN_F7R2_FB11 CAN_F7R2_FB11_Msk

#define	CAN_F7R2_FB12_Pos (12U)

#define	CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)

#define	CAN_F7R2_FB12 CAN_F7R2_FB12_Msk

#define	CAN_F7R2_FB13_Pos (13U)

#define	CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)

#define	CAN_F7R2_FB13 CAN_F7R2_FB13_Msk

#define	CAN_F7R2_FB14_Pos (14U)

#define	CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)

#define	CAN_F7R2_FB14 CAN_F7R2_FB14_Msk

#define	CAN_F7R2_FB15_Pos (15U)

#define	CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)

#define	CAN_F7R2_FB15 CAN_F7R2_FB15_Msk

#define	CAN_F7R2_FB16_Pos (16U)

#define	CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)

#define	CAN_F7R2_FB16 CAN_F7R2_FB16_Msk

#define	CAN_F7R2_FB17_Pos (17U)

#define	CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)

#define	CAN_F7R2_FB17 CAN_F7R2_FB17_Msk

#define	CAN_F7R2_FB18_Pos (18U)

#define	CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)

#define	CAN_F7R2_FB18 CAN_F7R2_FB18_Msk

#define	CAN_F7R2_FB19_Pos (19U)

#define	CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)

#define	CAN_F7R2_FB19 CAN_F7R2_FB19_Msk

#define	CAN_F7R2_FB20_Pos (20U)

#define	CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)

#define	CAN_F7R2_FB20 CAN_F7R2_FB20_Msk

#define	CAN_F7R2_FB21_Pos (21U)

#define	CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)

#define	CAN_F7R2_FB21 CAN_F7R2_FB21_Msk

#define	CAN_F7R2_FB22_Pos (22U)

#define	CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)

#define	CAN_F7R2_FB22 CAN_F7R2_FB22_Msk

#define	CAN_F7R2_FB23_Pos (23U)

#define	CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)

#define	CAN_F7R2_FB23 CAN_F7R2_FB23_Msk

#define	CAN_F7R2_FB24_Pos (24U)

#define	CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)

#define	CAN_F7R2_FB24 CAN_F7R2_FB24_Msk

#define	CAN_F7R2_FB25_Pos (25U)

#define	CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)

#define	CAN_F7R2_FB25 CAN_F7R2_FB25_Msk

#define	CAN_F7R2_FB26_Pos (26U)

#define	CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)

#define	CAN_F7R2_FB26 CAN_F7R2_FB26_Msk

#define	CAN_F7R2_FB27_Pos (27U)

#define	CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)

#define	CAN_F7R2_FB27 CAN_F7R2_FB27_Msk

#define	CAN_F7R2_FB28_Pos (28U)

#define	CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)

#define	CAN_F7R2_FB28 CAN_F7R2_FB28_Msk

#define	CAN_F7R2_FB29_Pos (29U)

#define	CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)

#define	CAN_F7R2_FB29 CAN_F7R2_FB29_Msk

#define	CAN_F7R2_FB30_Pos (30U)

#define	CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)

#define	CAN_F7R2_FB30 CAN_F7R2_FB30_Msk

#define	CAN_F7R2_FB31_Pos (31U)

#define	CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)

#define	CAN_F7R2_FB31 CAN_F7R2_FB31_Msk

#define	CAN_F8R2_FB0_Pos (0U)

#define	CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)

#define	CAN_F8R2_FB0 CAN_F8R2_FB0_Msk

#define	CAN_F8R2_FB1_Pos (1U)

#define	CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)

#define	CAN_F8R2_FB1 CAN_F8R2_FB1_Msk

#define	CAN_F8R2_FB2_Pos (2U)

#define	CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)

#define	CAN_F8R2_FB2 CAN_F8R2_FB2_Msk

#define	CAN_F8R2_FB3_Pos (3U)

#define	CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)

#define	CAN_F8R2_FB3 CAN_F8R2_FB3_Msk

#define	CAN_F8R2_FB4_Pos (4U)

#define	CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)

#define	CAN_F8R2_FB4 CAN_F8R2_FB4_Msk

#define	CAN_F8R2_FB5_Pos (5U)

#define	CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)

#define	CAN_F8R2_FB5 CAN_F8R2_FB5_Msk

#define	CAN_F8R2_FB6_Pos (6U)

#define	CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)

#define	CAN_F8R2_FB6 CAN_F8R2_FB6_Msk

#define	CAN_F8R2_FB7_Pos (7U)

#define	CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)

#define	CAN_F8R2_FB7 CAN_F8R2_FB7_Msk

#define	CAN_F8R2_FB8_Pos (8U)

#define	CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)

#define	CAN_F8R2_FB8 CAN_F8R2_FB8_Msk

#define	CAN_F8R2_FB9_Pos (9U)

#define	CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)

#define	CAN_F8R2_FB9 CAN_F8R2_FB9_Msk

#define	CAN_F8R2_FB10_Pos (10U)

#define	CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)

#define	CAN_F8R2_FB10 CAN_F8R2_FB10_Msk

#define	CAN_F8R2_FB11_Pos (11U)

#define	CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)

#define	CAN_F8R2_FB11 CAN_F8R2_FB11_Msk

#define	CAN_F8R2_FB12_Pos (12U)

#define	CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)

#define	CAN_F8R2_FB12 CAN_F8R2_FB12_Msk

#define	CAN_F8R2_FB13_Pos (13U)

#define	CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)

#define	CAN_F8R2_FB13 CAN_F8R2_FB13_Msk

#define	CAN_F8R2_FB14_Pos (14U)

#define	CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)

#define	CAN_F8R2_FB14 CAN_F8R2_FB14_Msk

#define	CAN_F8R2_FB15_Pos (15U)

#define	CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)

#define	CAN_F8R2_FB15 CAN_F8R2_FB15_Msk

#define	CAN_F8R2_FB16_Pos (16U)

#define	CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)

#define	CAN_F8R2_FB16 CAN_F8R2_FB16_Msk

#define	CAN_F8R2_FB17_Pos (17U)

#define	CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)

#define	CAN_F8R2_FB17 CAN_F8R2_FB17_Msk

#define	CAN_F8R2_FB18_Pos (18U)

#define	CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)

#define	CAN_F8R2_FB18 CAN_F8R2_FB18_Msk

#define	CAN_F8R2_FB19_Pos (19U)

#define	CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)

#define	CAN_F8R2_FB19 CAN_F8R2_FB19_Msk

#define	CAN_F8R2_FB20_Pos (20U)

#define	CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)

#define	CAN_F8R2_FB20 CAN_F8R2_FB20_Msk

#define	CAN_F8R2_FB21_Pos (21U)

#define	CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)

#define	CAN_F8R2_FB21 CAN_F8R2_FB21_Msk

#define	CAN_F8R2_FB22_Pos (22U)

#define	CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)

#define	CAN_F8R2_FB22 CAN_F8R2_FB22_Msk

#define	CAN_F8R2_FB23_Pos (23U)

#define	CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)

#define	CAN_F8R2_FB23 CAN_F8R2_FB23_Msk

#define	CAN_F8R2_FB24_Pos (24U)

#define	CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)

#define	CAN_F8R2_FB24 CAN_F8R2_FB24_Msk

#define	CAN_F8R2_FB25_Pos (25U)

#define	CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)

#define	CAN_F8R2_FB25 CAN_F8R2_FB25_Msk

#define	CAN_F8R2_FB26_Pos (26U)

#define	CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)

#define	CAN_F8R2_FB26 CAN_F8R2_FB26_Msk

#define	CAN_F8R2_FB27_Pos (27U)

#define	CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)

#define	CAN_F8R2_FB27 CAN_F8R2_FB27_Msk

#define	CAN_F8R2_FB28_Pos (28U)

#define	CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)

#define	CAN_F8R2_FB28 CAN_F8R2_FB28_Msk

#define	CAN_F8R2_FB29_Pos (29U)

#define	CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)

#define	CAN_F8R2_FB29 CAN_F8R2_FB29_Msk

#define	CAN_F8R2_FB30_Pos (30U)

#define	CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)

#define	CAN_F8R2_FB30 CAN_F8R2_FB30_Msk

#define	CAN_F8R2_FB31_Pos (31U)

#define	CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)

#define	CAN_F8R2_FB31 CAN_F8R2_FB31_Msk

#define	CAN_F9R2_FB0_Pos (0U)

#define	CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)

#define	CAN_F9R2_FB0 CAN_F9R2_FB0_Msk

#define	CAN_F9R2_FB1_Pos (1U)

#define	CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)

#define	CAN_F9R2_FB1 CAN_F9R2_FB1_Msk

#define	CAN_F9R2_FB2_Pos (2U)

#define	CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)

#define	CAN_F9R2_FB2 CAN_F9R2_FB2_Msk

#define	CAN_F9R2_FB3_Pos (3U)

#define	CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)

#define	CAN_F9R2_FB3 CAN_F9R2_FB3_Msk

#define	CAN_F9R2_FB4_Pos (4U)

#define	CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)

#define	CAN_F9R2_FB4 CAN_F9R2_FB4_Msk

#define	CAN_F9R2_FB5_Pos (5U)

#define	CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)

#define	CAN_F9R2_FB5 CAN_F9R2_FB5_Msk

#define	CAN_F9R2_FB6_Pos (6U)

#define	CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)

#define	CAN_F9R2_FB6 CAN_F9R2_FB6_Msk

#define	CAN_F9R2_FB7_Pos (7U)

#define	CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)

#define	CAN_F9R2_FB7 CAN_F9R2_FB7_Msk

#define	CAN_F9R2_FB8_Pos (8U)

#define	CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)

#define	CAN_F9R2_FB8 CAN_F9R2_FB8_Msk

#define	CAN_F9R2_FB9_Pos (9U)

#define	CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)

#define	CAN_F9R2_FB9 CAN_F9R2_FB9_Msk

#define	CAN_F9R2_FB10_Pos (10U)

#define	CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)

#define	CAN_F9R2_FB10 CAN_F9R2_FB10_Msk

#define	CAN_F9R2_FB11_Pos (11U)

#define	CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)

#define	CAN_F9R2_FB11 CAN_F9R2_FB11_Msk

#define	CAN_F9R2_FB12_Pos (12U)

#define	CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)

#define	CAN_F9R2_FB12 CAN_F9R2_FB12_Msk

#define	CAN_F9R2_FB13_Pos (13U)

#define	CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)

#define	CAN_F9R2_FB13 CAN_F9R2_FB13_Msk

#define	CAN_F9R2_FB14_Pos (14U)

#define	CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)

#define	CAN_F9R2_FB14 CAN_F9R2_FB14_Msk

#define	CAN_F9R2_FB15_Pos (15U)

#define	CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)

#define	CAN_F9R2_FB15 CAN_F9R2_FB15_Msk

#define	CAN_F9R2_FB16_Pos (16U)

#define	CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)

#define	CAN_F9R2_FB16 CAN_F9R2_FB16_Msk

#define	CAN_F9R2_FB17_Pos (17U)

#define	CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)

#define	CAN_F9R2_FB17 CAN_F9R2_FB17_Msk

#define	CAN_F9R2_FB18_Pos (18U)

#define	CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)

#define	CAN_F9R2_FB18 CAN_F9R2_FB18_Msk

#define	CAN_F9R2_FB19_Pos (19U)

#define	CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)

#define	CAN_F9R2_FB19 CAN_F9R2_FB19_Msk

#define	CAN_F9R2_FB20_Pos (20U)

#define	CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)

#define	CAN_F9R2_FB20 CAN_F9R2_FB20_Msk

#define	CAN_F9R2_FB21_Pos (21U)

#define	CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)

#define	CAN_F9R2_FB21 CAN_F9R2_FB21_Msk

#define	CAN_F9R2_FB22_Pos (22U)

#define	CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)

#define	CAN_F9R2_FB22 CAN_F9R2_FB22_Msk

#define	CAN_F9R2_FB23_Pos (23U)

#define	CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)

#define	CAN_F9R2_FB23 CAN_F9R2_FB23_Msk

#define	CAN_F9R2_FB24_Pos (24U)

#define	CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)

#define	CAN_F9R2_FB24 CAN_F9R2_FB24_Msk

#define	CAN_F9R2_FB25_Pos (25U)

#define	CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)

#define	CAN_F9R2_FB25 CAN_F9R2_FB25_Msk

#define	CAN_F9R2_FB26_Pos (26U)

#define	CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)

#define	CAN_F9R2_FB26 CAN_F9R2_FB26_Msk

#define	CAN_F9R2_FB27_Pos (27U)

#define	CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)

#define	CAN_F9R2_FB27 CAN_F9R2_FB27_Msk

#define	CAN_F9R2_FB28_Pos (28U)

#define	CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)

#define	CAN_F9R2_FB28 CAN_F9R2_FB28_Msk

#define	CAN_F9R2_FB29_Pos (29U)

#define	CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)

#define	CAN_F9R2_FB29 CAN_F9R2_FB29_Msk

#define	CAN_F9R2_FB30_Pos (30U)

#define	CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)

#define	CAN_F9R2_FB30 CAN_F9R2_FB30_Msk

#define	CAN_F9R2_FB31_Pos (31U)

#define	CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)

#define	CAN_F9R2_FB31 CAN_F9R2_FB31_Msk

#define	CAN_F10R2_FB0_Pos (0U)

#define	CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)

#define	CAN_F10R2_FB0 CAN_F10R2_FB0_Msk

#define	CAN_F10R2_FB1_Pos (1U)

#define	CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)

#define	CAN_F10R2_FB1 CAN_F10R2_FB1_Msk

#define	CAN_F10R2_FB2_Pos (2U)

#define	CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)

#define	CAN_F10R2_FB2 CAN_F10R2_FB2_Msk

#define	CAN_F10R2_FB3_Pos (3U)

#define	CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)

#define	CAN_F10R2_FB3 CAN_F10R2_FB3_Msk

#define	CAN_F10R2_FB4_Pos (4U)

#define	CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)

#define	CAN_F10R2_FB4 CAN_F10R2_FB4_Msk

#define	CAN_F10R2_FB5_Pos (5U)

#define	CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)

#define	CAN_F10R2_FB5 CAN_F10R2_FB5_Msk

#define	CAN_F10R2_FB6_Pos (6U)

#define	CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)

#define	CAN_F10R2_FB6 CAN_F10R2_FB6_Msk

#define	CAN_F10R2_FB7_Pos (7U)

#define	CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)

#define	CAN_F10R2_FB7 CAN_F10R2_FB7_Msk

#define	CAN_F10R2_FB8_Pos (8U)

#define	CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)

#define	CAN_F10R2_FB8 CAN_F10R2_FB8_Msk

#define	CAN_F10R2_FB9_Pos (9U)

#define	CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)

#define	CAN_F10R2_FB9 CAN_F10R2_FB9_Msk

#define	CAN_F10R2_FB10_Pos (10U)

#define	CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)

#define	CAN_F10R2_FB10 CAN_F10R2_FB10_Msk

#define	CAN_F10R2_FB11_Pos (11U)

#define	CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)

#define	CAN_F10R2_FB11 CAN_F10R2_FB11_Msk

#define	CAN_F10R2_FB12_Pos (12U)

#define	CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)

#define	CAN_F10R2_FB12 CAN_F10R2_FB12_Msk

#define	CAN_F10R2_FB13_Pos (13U)

#define	CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)

#define	CAN_F10R2_FB13 CAN_F10R2_FB13_Msk

#define	CAN_F10R2_FB14_Pos (14U)

#define	CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)

#define	CAN_F10R2_FB14 CAN_F10R2_FB14_Msk

#define	CAN_F10R2_FB15_Pos (15U)

#define	CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)

#define	CAN_F10R2_FB15 CAN_F10R2_FB15_Msk

#define	CAN_F10R2_FB16_Pos (16U)

#define	CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)

#define	CAN_F10R2_FB16 CAN_F10R2_FB16_Msk

#define	CAN_F10R2_FB17_Pos (17U)

#define	CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)

#define	CAN_F10R2_FB17 CAN_F10R2_FB17_Msk

#define	CAN_F10R2_FB18_Pos (18U)

#define	CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)

#define	CAN_F10R2_FB18 CAN_F10R2_FB18_Msk

#define	CAN_F10R2_FB19_Pos (19U)

#define	CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)

#define	CAN_F10R2_FB19 CAN_F10R2_FB19_Msk

#define	CAN_F10R2_FB20_Pos (20U)

#define	CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)

#define	CAN_F10R2_FB20 CAN_F10R2_FB20_Msk

#define	CAN_F10R2_FB21_Pos (21U)

#define	CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)

#define	CAN_F10R2_FB21 CAN_F10R2_FB21_Msk

#define	CAN_F10R2_FB22_Pos (22U)

#define	CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)

#define	CAN_F10R2_FB22 CAN_F10R2_FB22_Msk

#define	CAN_F10R2_FB23_Pos (23U)

#define	CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)

#define	CAN_F10R2_FB23 CAN_F10R2_FB23_Msk

#define	CAN_F10R2_FB24_Pos (24U)

#define	CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)

#define	CAN_F10R2_FB24 CAN_F10R2_FB24_Msk

#define	CAN_F10R2_FB25_Pos (25U)

#define	CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)

#define	CAN_F10R2_FB25 CAN_F10R2_FB25_Msk

#define	CAN_F10R2_FB26_Pos (26U)

#define	CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)

#define	CAN_F10R2_FB26 CAN_F10R2_FB26_Msk

#define	CAN_F10R2_FB27_Pos (27U)

#define	CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)

#define	CAN_F10R2_FB27 CAN_F10R2_FB27_Msk

#define	CAN_F10R2_FB28_Pos (28U)

#define	CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)

#define	CAN_F10R2_FB28 CAN_F10R2_FB28_Msk

#define	CAN_F10R2_FB29_Pos (29U)

#define	CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)

#define	CAN_F10R2_FB29 CAN_F10R2_FB29_Msk

#define	CAN_F10R2_FB30_Pos (30U)

#define	CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)

#define	CAN_F10R2_FB30 CAN_F10R2_FB30_Msk

#define	CAN_F10R2_FB31_Pos (31U)

#define	CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)

#define	CAN_F10R2_FB31 CAN_F10R2_FB31_Msk

#define	CAN_F11R2_FB0_Pos (0U)

#define	CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)

#define	CAN_F11R2_FB0 CAN_F11R2_FB0_Msk

#define	CAN_F11R2_FB1_Pos (1U)

#define	CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)

#define	CAN_F11R2_FB1 CAN_F11R2_FB1_Msk

#define	CAN_F11R2_FB2_Pos (2U)

#define	CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)

#define	CAN_F11R2_FB2 CAN_F11R2_FB2_Msk

#define	CAN_F11R2_FB3_Pos (3U)

#define	CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)

#define	CAN_F11R2_FB3 CAN_F11R2_FB3_Msk

#define	CAN_F11R2_FB4_Pos (4U)

#define	CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)

#define	CAN_F11R2_FB4 CAN_F11R2_FB4_Msk

#define	CAN_F11R2_FB5_Pos (5U)

#define	CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)

#define	CAN_F11R2_FB5 CAN_F11R2_FB5_Msk

#define	CAN_F11R2_FB6_Pos (6U)

#define	CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)

#define	CAN_F11R2_FB6 CAN_F11R2_FB6_Msk

#define	CAN_F11R2_FB7_Pos (7U)

#define	CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)

#define	CAN_F11R2_FB7 CAN_F11R2_FB7_Msk

#define	CAN_F11R2_FB8_Pos (8U)

#define	CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)

#define	CAN_F11R2_FB8 CAN_F11R2_FB8_Msk

#define	CAN_F11R2_FB9_Pos (9U)

#define	CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)

#define	CAN_F11R2_FB9 CAN_F11R2_FB9_Msk

#define	CAN_F11R2_FB10_Pos (10U)

#define	CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)

#define	CAN_F11R2_FB10 CAN_F11R2_FB10_Msk

#define	CAN_F11R2_FB11_Pos (11U)

#define	CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)

#define	CAN_F11R2_FB11 CAN_F11R2_FB11_Msk

#define	CAN_F11R2_FB12_Pos (12U)

#define	CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)

#define	CAN_F11R2_FB12 CAN_F11R2_FB12_Msk

#define	CAN_F11R2_FB13_Pos (13U)

#define	CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)

#define	CAN_F11R2_FB13 CAN_F11R2_FB13_Msk

#define	CAN_F11R2_FB14_Pos (14U)

#define	CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)

#define	CAN_F11R2_FB14 CAN_F11R2_FB14_Msk

#define	CAN_F11R2_FB15_Pos (15U)

#define	CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)

#define	CAN_F11R2_FB15 CAN_F11R2_FB15_Msk

#define	CAN_F11R2_FB16_Pos (16U)

#define	CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)

#define	CAN_F11R2_FB16 CAN_F11R2_FB16_Msk

#define	CAN_F11R2_FB17_Pos (17U)

#define	CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)

#define	CAN_F11R2_FB17 CAN_F11R2_FB17_Msk

#define	CAN_F11R2_FB18_Pos (18U)

#define	CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)

#define	CAN_F11R2_FB18 CAN_F11R2_FB18_Msk

#define	CAN_F11R2_FB19_Pos (19U)

#define	CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)

#define	CAN_F11R2_FB19 CAN_F11R2_FB19_Msk

#define	CAN_F11R2_FB20_Pos (20U)

#define	CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)

#define	CAN_F11R2_FB20 CAN_F11R2_FB20_Msk

#define	CAN_F11R2_FB21_Pos (21U)

#define	CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)

#define	CAN_F11R2_FB21 CAN_F11R2_FB21_Msk

#define	CAN_F11R2_FB22_Pos (22U)

#define	CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)

#define	CAN_F11R2_FB22 CAN_F11R2_FB22_Msk

#define	CAN_F11R2_FB23_Pos (23U)

#define	CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)

#define	CAN_F11R2_FB23 CAN_F11R2_FB23_Msk

#define	CAN_F11R2_FB24_Pos (24U)

#define	CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)

#define	CAN_F11R2_FB24 CAN_F11R2_FB24_Msk

#define	CAN_F11R2_FB25_Pos (25U)

#define	CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)

#define	CAN_F11R2_FB25 CAN_F11R2_FB25_Msk

#define	CAN_F11R2_FB26_Pos (26U)

#define	CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)

#define	CAN_F11R2_FB26 CAN_F11R2_FB26_Msk

#define	CAN_F11R2_FB27_Pos (27U)

#define	CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)

#define	CAN_F11R2_FB27 CAN_F11R2_FB27_Msk

#define	CAN_F11R2_FB28_Pos (28U)

#define	CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)

#define	CAN_F11R2_FB28 CAN_F11R2_FB28_Msk

#define	CAN_F11R2_FB29_Pos (29U)

#define	CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)

#define	CAN_F11R2_FB29 CAN_F11R2_FB29_Msk

#define	CAN_F11R2_FB30_Pos (30U)

#define	CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)

#define	CAN_F11R2_FB30 CAN_F11R2_FB30_Msk

#define	CAN_F11R2_FB31_Pos (31U)

#define	CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)

#define	CAN_F11R2_FB31 CAN_F11R2_FB31_Msk

#define	CAN_F12R2_FB0_Pos (0U)

#define	CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)

#define	CAN_F12R2_FB0 CAN_F12R2_FB0_Msk

#define	CAN_F12R2_FB1_Pos (1U)

#define	CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)

#define	CAN_F12R2_FB1 CAN_F12R2_FB1_Msk

#define	CAN_F12R2_FB2_Pos (2U)

#define	CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)

#define	CAN_F12R2_FB2 CAN_F12R2_FB2_Msk

#define	CAN_F12R2_FB3_Pos (3U)

#define	CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)

#define	CAN_F12R2_FB3 CAN_F12R2_FB3_Msk

#define	CAN_F12R2_FB4_Pos (4U)

#define	CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)

#define	CAN_F12R2_FB4 CAN_F12R2_FB4_Msk

#define	CAN_F12R2_FB5_Pos (5U)

#define	CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)

#define	CAN_F12R2_FB5 CAN_F12R2_FB5_Msk

#define	CAN_F12R2_FB6_Pos (6U)

#define	CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)

#define	CAN_F12R2_FB6 CAN_F12R2_FB6_Msk

#define	CAN_F12R2_FB7_Pos (7U)

#define	CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)

#define	CAN_F12R2_FB7 CAN_F12R2_FB7_Msk

#define	CAN_F12R2_FB8_Pos (8U)

#define	CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)

#define	CAN_F12R2_FB8 CAN_F12R2_FB8_Msk

#define	CAN_F12R2_FB9_Pos (9U)

#define	CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)

#define	CAN_F12R2_FB9 CAN_F12R2_FB9_Msk

#define	CAN_F12R2_FB10_Pos (10U)

#define	CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)

#define	CAN_F12R2_FB10 CAN_F12R2_FB10_Msk

#define	CAN_F12R2_FB11_Pos (11U)

#define	CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)

#define	CAN_F12R2_FB11 CAN_F12R2_FB11_Msk

#define	CAN_F12R2_FB12_Pos (12U)

#define	CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)

#define	CAN_F12R2_FB12 CAN_F12R2_FB12_Msk

#define	CAN_F12R2_FB13_Pos (13U)

#define	CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)

#define	CAN_F12R2_FB13 CAN_F12R2_FB13_Msk

#define	CAN_F12R2_FB14_Pos (14U)

#define	CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)

#define	CAN_F12R2_FB14 CAN_F12R2_FB14_Msk

#define	CAN_F12R2_FB15_Pos (15U)

#define	CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)

#define	CAN_F12R2_FB15 CAN_F12R2_FB15_Msk

#define	CAN_F12R2_FB16_Pos (16U)

#define	CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)

#define	CAN_F12R2_FB16 CAN_F12R2_FB16_Msk

#define	CAN_F12R2_FB17_Pos (17U)

#define	CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)

#define	CAN_F12R2_FB17 CAN_F12R2_FB17_Msk

#define	CAN_F12R2_FB18_Pos (18U)

#define	CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)

#define	CAN_F12R2_FB18 CAN_F12R2_FB18_Msk

#define	CAN_F12R2_FB19_Pos (19U)

#define	CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)

#define	CAN_F12R2_FB19 CAN_F12R2_FB19_Msk

#define	CAN_F12R2_FB20_Pos (20U)

#define	CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)

#define	CAN_F12R2_FB20 CAN_F12R2_FB20_Msk

#define	CAN_F12R2_FB21_Pos (21U)

#define	CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)

#define	CAN_F12R2_FB21 CAN_F12R2_FB21_Msk

#define	CAN_F12R2_FB22_Pos (22U)

#define	CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)

#define	CAN_F12R2_FB22 CAN_F12R2_FB22_Msk

#define	CAN_F12R2_FB23_Pos (23U)

#define	CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)

#define	CAN_F12R2_FB23 CAN_F12R2_FB23_Msk

#define	CAN_F12R2_FB24_Pos (24U)

#define	CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)

#define	CAN_F12R2_FB24 CAN_F12R2_FB24_Msk

#define	CAN_F12R2_FB25_Pos (25U)

#define	CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)

#define	CAN_F12R2_FB25 CAN_F12R2_FB25_Msk

#define	CAN_F12R2_FB26_Pos (26U)

#define	CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)

#define	CAN_F12R2_FB26 CAN_F12R2_FB26_Msk

#define	CAN_F12R2_FB27_Pos (27U)

#define	CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)

#define	CAN_F12R2_FB27 CAN_F12R2_FB27_Msk

#define	CAN_F12R2_FB28_Pos (28U)

#define	CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)

#define	CAN_F12R2_FB28 CAN_F12R2_FB28_Msk

#define	CAN_F12R2_FB29_Pos (29U)

#define	CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)

#define	CAN_F12R2_FB29 CAN_F12R2_FB29_Msk

#define	CAN_F12R2_FB30_Pos (30U)

#define	CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)

#define	CAN_F12R2_FB30 CAN_F12R2_FB30_Msk

#define	CAN_F12R2_FB31_Pos (31U)

#define	CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)

#define	CAN_F12R2_FB31 CAN_F12R2_FB31_Msk

#define	CAN_F13R2_FB0_Pos (0U)

#define	CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)

#define	CAN_F13R2_FB0 CAN_F13R2_FB0_Msk

#define	CAN_F13R2_FB1_Pos (1U)

#define	CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)

#define	CAN_F13R2_FB1 CAN_F13R2_FB1_Msk

#define	CAN_F13R2_FB2_Pos (2U)

#define	CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)

#define	CAN_F13R2_FB2 CAN_F13R2_FB2_Msk

#define	CAN_F13R2_FB3_Pos (3U)

#define	CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)

#define	CAN_F13R2_FB3 CAN_F13R2_FB3_Msk

#define	CAN_F13R2_FB4_Pos (4U)

#define	CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)

#define	CAN_F13R2_FB4 CAN_F13R2_FB4_Msk

#define	CAN_F13R2_FB5_Pos (5U)

#define	CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)

#define	CAN_F13R2_FB5 CAN_F13R2_FB5_Msk

#define	CAN_F13R2_FB6_Pos (6U)

#define	CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)

#define	CAN_F13R2_FB6 CAN_F13R2_FB6_Msk

#define	CAN_F13R2_FB7_Pos (7U)

#define	CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)

#define	CAN_F13R2_FB7 CAN_F13R2_FB7_Msk

#define	CAN_F13R2_FB8_Pos (8U)

#define	CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)

#define	CAN_F13R2_FB8 CAN_F13R2_FB8_Msk

#define	CAN_F13R2_FB9_Pos (9U)

#define	CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)

#define	CAN_F13R2_FB9 CAN_F13R2_FB9_Msk

#define	CAN_F13R2_FB10_Pos (10U)

#define	CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)

#define	CAN_F13R2_FB10 CAN_F13R2_FB10_Msk

#define	CAN_F13R2_FB11_Pos (11U)

#define	CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)

#define	CAN_F13R2_FB11 CAN_F13R2_FB11_Msk

#define	CAN_F13R2_FB12_Pos (12U)

#define	CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)

#define	CAN_F13R2_FB12 CAN_F13R2_FB12_Msk

#define	CAN_F13R2_FB13_Pos (13U)

#define	CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)

#define	CAN_F13R2_FB13 CAN_F13R2_FB13_Msk

#define	CAN_F13R2_FB14_Pos (14U)

#define	CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)

#define	CAN_F13R2_FB14 CAN_F13R2_FB14_Msk

#define	CAN_F13R2_FB15_Pos (15U)

#define	CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)

#define	CAN_F13R2_FB15 CAN_F13R2_FB15_Msk

#define	CAN_F13R2_FB16_Pos (16U)

#define	CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)

#define	CAN_F13R2_FB16 CAN_F13R2_FB16_Msk

#define	CAN_F13R2_FB17_Pos (17U)

#define	CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)

#define	CAN_F13R2_FB17 CAN_F13R2_FB17_Msk

#define	CAN_F13R2_FB18_Pos (18U)

#define	CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)

#define	CAN_F13R2_FB18 CAN_F13R2_FB18_Msk

#define	CAN_F13R2_FB19_Pos (19U)

#define	CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)

#define	CAN_F13R2_FB19 CAN_F13R2_FB19_Msk

#define	CAN_F13R2_FB20_Pos (20U)

#define	CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)

#define	CAN_F13R2_FB20 CAN_F13R2_FB20_Msk

#define	CAN_F13R2_FB21_Pos (21U)

#define	CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)

#define	CAN_F13R2_FB21 CAN_F13R2_FB21_Msk

#define	CAN_F13R2_FB22_Pos (22U)

#define	CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)

#define	CAN_F13R2_FB22 CAN_F13R2_FB22_Msk

#define	CAN_F13R2_FB23_Pos (23U)

#define	CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)

#define	CAN_F13R2_FB23 CAN_F13R2_FB23_Msk

#define	CAN_F13R2_FB24_Pos (24U)

#define	CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)

#define	CAN_F13R2_FB24 CAN_F13R2_FB24_Msk

#define	CAN_F13R2_FB25_Pos (25U)

#define	CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)

#define	CAN_F13R2_FB25 CAN_F13R2_FB25_Msk

#define	CAN_F13R2_FB26_Pos (26U)

#define	CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)

#define	CAN_F13R2_FB26 CAN_F13R2_FB26_Msk

#define	CAN_F13R2_FB27_Pos (27U)

#define	CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)

#define	CAN_F13R2_FB27 CAN_F13R2_FB27_Msk

#define	CAN_F13R2_FB28_Pos (28U)

#define	CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)

#define	CAN_F13R2_FB28 CAN_F13R2_FB28_Msk

#define	CAN_F13R2_FB29_Pos (29U)

#define	CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)

#define	CAN_F13R2_FB29 CAN_F13R2_FB29_Msk

#define	CAN_F13R2_FB30_Pos (30U)

#define	CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)

#define	CAN_F13R2_FB30 CAN_F13R2_FB30_Msk

#define	CAN_F13R2_FB31_Pos (31U)

#define	CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)

#define	CAN_F13R2_FB31 CAN_F13R2_FB31_Msk

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR ((uint8_t)0xFFU)

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	CRC_CR_POLYSIZE_Pos (3U)

#define	CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

#define	CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_REV_IN_Pos (5U)

#define	CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN CRC_CR_REV_IN_Msk

#define	CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_OUT_Pos (7U)

#define	CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

#define	CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

#define	CRC_INIT_INIT_Pos (0U)

#define	CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

#define	CRC_INIT_INIT CRC_INIT_INIT_Msk

#define	CRC_POL_POL_Pos (0U)

#define	CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

#define	CRC_POL_POL CRC_POL_POL_Msk

#define	DAC_CHANNEL2_SUPPORT

#define	DAC_CR_EN1_Pos (0U)

#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

#define	DAC_CR_EN1 DAC_CR_EN1_Msk

#define	DAC_CR_BOFF1_Pos (1U)

#define	DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)

#define	DAC_CR_BOFF1 DAC_CR_BOFF1_Msk

#define	DAC_CR_OUTEN1_Pos (1U)

#define	DAC_CR_OUTEN1_Msk (0x1UL << DAC_CR_OUTEN1_Pos)

#define	DAC_CR_OUTEN1 DAC_CR_OUTEN1_Msk

#define	DAC_CR_TEN1_Pos (2U)

#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk

#define	DAC_CR_TSEL1_Pos (3U)

#define	DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_WAVE1_Pos (6U)

#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_MAMP1_Pos (8U)

#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_DMAEN1_Pos (12U)

#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

#define	DAC_CR_DMAUDRIE1_Pos (13U)

#define	DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

#define	DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

#define	DAC_CR_EN2_Pos (16U)

#define	DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

#define	DAC_CR_EN2 DAC_CR_EN2_Msk

#define	DAC_CR_BOFF2_Pos (17U)

#define	DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)

#define	DAC_CR_BOFF2 DAC_CR_BOFF2_Msk

#define	DAC_CR_OUTEN2_Pos (17U)

#define	DAC_CR_OUTEN2_Msk (0x1UL << DAC_CR_OUTEN2_Pos)

#define	DAC_CR_OUTEN2 DAC_CR_OUTEN2_Msk

#define	DAC_CR_TEN2_Pos (18U)

#define	DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

#define	DAC_CR_TEN2 DAC_CR_TEN2_Msk

#define	DAC_CR_TSEL2_Pos (19U)

#define	DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

#define	DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_WAVE2_Pos (22U)

#define	DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

#define	DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_MAMP2_Pos (24U)

#define	DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

#define	DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_DMAEN2_Pos (28U)

#define	DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

#define	DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

#define	DAC_CR_DMAUDRIE2_Pos (29U)

#define	DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

#define	DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)

#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

#define	DAC_SWTRIGR_SWTRIG2_Pos (1U)

#define	DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

#define	DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

#define	DAC_DHR12R1_DACC1DHR_Pos (0U)

#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

#define	DAC_DHR12L1_DACC1DHR_Pos (4U)

#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

#define	DAC_DHR8R1_DACC1DHR_Pos (0U)

#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

#define	DAC_DHR12R2_DACC2DHR_Pos (0U)

#define	DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

#define	DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

#define	DAC_DHR12L2_DACC2DHR_Pos (4U)

#define	DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

#define	DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

#define	DAC_DHR8R2_DACC2DHR_Pos (0U)

#define	DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

#define	DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

#define	DAC_DHR12RD_DACC1DHR_Pos (0U)

#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

#define	DAC_DHR12RD_DACC2DHR_Pos (16U)

#define	DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

#define	DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

#define	DAC_DHR12LD_DACC1DHR_Pos (4U)

#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

#define	DAC_DHR12LD_DACC2DHR_Pos (20U)

#define	DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

#define	DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

#define	DAC_DHR8RD_DACC1DHR_Pos (0U)

#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

#define	DAC_DHR8RD_DACC2DHR_Pos (8U)

#define	DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

#define	DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

#define	DAC_DOR1_DACC1DOR_Pos (0U)

#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

#define	DAC_DOR2_DACC2DOR_Pos (0U)

#define	DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

#define	DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

#define	DAC_SR_DMAUDR1_Pos (13U)

#define	DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

#define	DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

#define	DAC_SR_DMAUDR2_Pos (29U)

#define	DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

#define	DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)

#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_Pos (16U)

#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)

#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

#define	DBGMCU_CR_DBG_STOP_Pos (1U)

#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)

#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

#define	DBGMCU_CR_TRACE_IOEN_Pos (5U)

#define	DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

#define	DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

#define	DBGMCU_CR_TRACE_MODE_Pos (6U)

#define	DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

#define	DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos (8U)

#define	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_ISR_GIF7_Pos (24U)

#define	DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

#define	DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

#define	DMA_ISR_TCIF7_Pos (25U)

#define	DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

#define	DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

#define	DMA_ISR_HTIF7_Pos (26U)

#define	DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

#define	DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

#define	DMA_ISR_TEIF7_Pos (27U)

#define	DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

#define	DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_IFCR_CGIF7_Pos (24U)

#define	DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

#define	DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

#define	DMA_IFCR_CTCIF7_Pos (25U)

#define	DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

#define	DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

#define	DMA_IFCR_CHTIF7_Pos (26U)

#define	DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

#define	DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

#define	DMA_IFCR_CTEIF7_Pos (27U)

#define	DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

#define	DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	EXTI_IMR_MR0_Pos (0U)

#define	EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)

#define	EXTI_IMR_MR0 EXTI_IMR_MR0_Msk

#define	EXTI_IMR_MR1_Pos (1U)

#define	EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)

#define	EXTI_IMR_MR1 EXTI_IMR_MR1_Msk

#define	EXTI_IMR_MR2_Pos (2U)

#define	EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)

#define	EXTI_IMR_MR2 EXTI_IMR_MR2_Msk

#define	EXTI_IMR_MR3_Pos (3U)

#define	EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)

#define	EXTI_IMR_MR3 EXTI_IMR_MR3_Msk

#define	EXTI_IMR_MR4_Pos (4U)

#define	EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)

#define	EXTI_IMR_MR4 EXTI_IMR_MR4_Msk

#define	EXTI_IMR_MR5_Pos (5U)

#define	EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)

#define	EXTI_IMR_MR5 EXTI_IMR_MR5_Msk

#define	EXTI_IMR_MR6_Pos (6U)

#define	EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)

#define	EXTI_IMR_MR6 EXTI_IMR_MR6_Msk

#define	EXTI_IMR_MR7_Pos (7U)

#define	EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)

#define	EXTI_IMR_MR7 EXTI_IMR_MR7_Msk

#define	EXTI_IMR_MR8_Pos (8U)

#define	EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)

#define	EXTI_IMR_MR8 EXTI_IMR_MR8_Msk

#define	EXTI_IMR_MR9_Pos (9U)

#define	EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)

#define	EXTI_IMR_MR9 EXTI_IMR_MR9_Msk

#define	EXTI_IMR_MR10_Pos (10U)

#define	EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)

#define	EXTI_IMR_MR10 EXTI_IMR_MR10_Msk

#define	EXTI_IMR_MR11_Pos (11U)

#define	EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)

#define	EXTI_IMR_MR11 EXTI_IMR_MR11_Msk

#define	EXTI_IMR_MR12_Pos (12U)

#define	EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)

#define	EXTI_IMR_MR12 EXTI_IMR_MR12_Msk

#define	EXTI_IMR_MR13_Pos (13U)

#define	EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)

#define	EXTI_IMR_MR13 EXTI_IMR_MR13_Msk

#define	EXTI_IMR_MR14_Pos (14U)

#define	EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)

#define	EXTI_IMR_MR14 EXTI_IMR_MR14_Msk

#define	EXTI_IMR_MR15_Pos (15U)

#define	EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)

#define	EXTI_IMR_MR15 EXTI_IMR_MR15_Msk

#define	EXTI_IMR_MR16_Pos (16U)

#define	EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)

#define	EXTI_IMR_MR16 EXTI_IMR_MR16_Msk

#define	EXTI_IMR_MR17_Pos (17U)

#define	EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)

#define	EXTI_IMR_MR17 EXTI_IMR_MR17_Msk

#define	EXTI_IMR_MR19_Pos (19U)

#define	EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)

#define	EXTI_IMR_MR19 EXTI_IMR_MR19_Msk

#define	EXTI_IMR_MR20_Pos (20U)

#define	EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)

#define	EXTI_IMR_MR20 EXTI_IMR_MR20_Msk

#define	EXTI_IMR_MR22_Pos (22U)

#define	EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)

#define	EXTI_IMR_MR22 EXTI_IMR_MR22_Msk

#define	EXTI_IMR_MR23_Pos (23U)

#define	EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)

#define	EXTI_IMR_MR23 EXTI_IMR_MR23_Msk

#define	EXTI_IMR_MR25_Pos (25U)

#define	EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos)

#define	EXTI_IMR_MR25 EXTI_IMR_MR25_Msk

#define	EXTI_IMR_MR30_Pos (30U)

#define	EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos)

#define	EXTI_IMR_MR30 EXTI_IMR_MR30_Msk

#define	EXTI_IMR_IM0 EXTI_IMR_MR0

#define	EXTI_IMR_IM1 EXTI_IMR_MR1

#define	EXTI_IMR_IM2 EXTI_IMR_MR2

#define	EXTI_IMR_IM3 EXTI_IMR_MR3

#define	EXTI_IMR_IM4 EXTI_IMR_MR4

#define	EXTI_IMR_IM5 EXTI_IMR_MR5

#define	EXTI_IMR_IM6 EXTI_IMR_MR6

#define	EXTI_IMR_IM7 EXTI_IMR_MR7

#define	EXTI_IMR_IM8 EXTI_IMR_MR8

#define	EXTI_IMR_IM9 EXTI_IMR_MR9

#define	EXTI_IMR_IM10 EXTI_IMR_MR10

#define	EXTI_IMR_IM11 EXTI_IMR_MR11

#define	EXTI_IMR_IM12 EXTI_IMR_MR12

#define	EXTI_IMR_IM13 EXTI_IMR_MR13

#define	EXTI_IMR_IM14 EXTI_IMR_MR14

#define	EXTI_IMR_IM15 EXTI_IMR_MR15

#define	EXTI_IMR_IM16 EXTI_IMR_MR16

#define	EXTI_IMR_IM17 EXTI_IMR_MR17

#define	EXTI_IMR_IM19 EXTI_IMR_MR19

#define	EXTI_IMR_IM20 EXTI_IMR_MR20

#define	EXTI_IMR_IM22 EXTI_IMR_MR22

#define	EXTI_IMR_IM23 EXTI_IMR_MR23

#define	EXTI_IMR_IM25 EXTI_IMR_MR25

#define	EXTI_IMR_IM30 EXTI_IMR_MR30

#define	EXTI_IMR_IM_Pos (0U)

#define	EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)

#define	EXTI_IMR_IM EXTI_IMR_IM_Msk

#define	EXTI_EMR_MR0_Pos (0U)

#define	EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)

#define	EXTI_EMR_MR0 EXTI_EMR_MR0_Msk

#define	EXTI_EMR_MR1_Pos (1U)

#define	EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)

#define	EXTI_EMR_MR1 EXTI_EMR_MR1_Msk

#define	EXTI_EMR_MR2_Pos (2U)

#define	EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)

#define	EXTI_EMR_MR2 EXTI_EMR_MR2_Msk

#define	EXTI_EMR_MR3_Pos (3U)

#define	EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)

#define	EXTI_EMR_MR3 EXTI_EMR_MR3_Msk

#define	EXTI_EMR_MR4_Pos (4U)

#define	EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)

#define	EXTI_EMR_MR4 EXTI_EMR_MR4_Msk

#define	EXTI_EMR_MR5_Pos (5U)

#define	EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)

#define	EXTI_EMR_MR5 EXTI_EMR_MR5_Msk

#define	EXTI_EMR_MR6_Pos (6U)

#define	EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)

#define	EXTI_EMR_MR6 EXTI_EMR_MR6_Msk

#define	EXTI_EMR_MR7_Pos (7U)

#define	EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)

#define	EXTI_EMR_MR7 EXTI_EMR_MR7_Msk

#define	EXTI_EMR_MR8_Pos (8U)

#define	EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)

#define	EXTI_EMR_MR8 EXTI_EMR_MR8_Msk

#define	EXTI_EMR_MR9_Pos (9U)

#define	EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)

#define	EXTI_EMR_MR9 EXTI_EMR_MR9_Msk

#define	EXTI_EMR_MR10_Pos (10U)

#define	EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)

#define	EXTI_EMR_MR10 EXTI_EMR_MR10_Msk

#define	EXTI_EMR_MR11_Pos (11U)

#define	EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)

#define	EXTI_EMR_MR11 EXTI_EMR_MR11_Msk

#define	EXTI_EMR_MR12_Pos (12U)

#define	EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)

#define	EXTI_EMR_MR12 EXTI_EMR_MR12_Msk

#define	EXTI_EMR_MR13_Pos (13U)

#define	EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)

#define	EXTI_EMR_MR13 EXTI_EMR_MR13_Msk

#define	EXTI_EMR_MR14_Pos (14U)

#define	EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)

#define	EXTI_EMR_MR14 EXTI_EMR_MR14_Msk

#define	EXTI_EMR_MR15_Pos (15U)

#define	EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)

#define	EXTI_EMR_MR15 EXTI_EMR_MR15_Msk

#define	EXTI_EMR_MR16_Pos (16U)

#define	EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)

#define	EXTI_EMR_MR16 EXTI_EMR_MR16_Msk

#define	EXTI_EMR_MR17_Pos (17U)

#define	EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)

#define	EXTI_EMR_MR17 EXTI_EMR_MR17_Msk

#define	EXTI_EMR_MR19_Pos (19U)

#define	EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)

#define	EXTI_EMR_MR19 EXTI_EMR_MR19_Msk

#define	EXTI_EMR_MR20_Pos (20U)

#define	EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)

#define	EXTI_EMR_MR20 EXTI_EMR_MR20_Msk

#define	EXTI_EMR_MR22_Pos (22U)

#define	EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)

#define	EXTI_EMR_MR22 EXTI_EMR_MR22_Msk

#define	EXTI_EMR_MR23_Pos (23U)

#define	EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)

#define	EXTI_EMR_MR23 EXTI_EMR_MR23_Msk

#define	EXTI_EMR_MR25_Pos (25U)

#define	EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos)

#define	EXTI_EMR_MR25 EXTI_EMR_MR25_Msk

#define	EXTI_EMR_MR30_Pos (30U)

#define	EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos)

#define	EXTI_EMR_MR30 EXTI_EMR_MR30_Msk

#define	EXTI_EMR_EM0 EXTI_EMR_MR0

#define	EXTI_EMR_EM1 EXTI_EMR_MR1

#define	EXTI_EMR_EM2 EXTI_EMR_MR2

#define	EXTI_EMR_EM3 EXTI_EMR_MR3

#define	EXTI_EMR_EM4 EXTI_EMR_MR4

#define	EXTI_EMR_EM5 EXTI_EMR_MR5

#define	EXTI_EMR_EM6 EXTI_EMR_MR6

#define	EXTI_EMR_EM7 EXTI_EMR_MR7

#define	EXTI_EMR_EM8 EXTI_EMR_MR8

#define	EXTI_EMR_EM9 EXTI_EMR_MR9

#define	EXTI_EMR_EM10 EXTI_EMR_MR10

#define	EXTI_EMR_EM11 EXTI_EMR_MR11

#define	EXTI_EMR_EM12 EXTI_EMR_MR12

#define	EXTI_EMR_EM13 EXTI_EMR_MR13

#define	EXTI_EMR_EM14 EXTI_EMR_MR14

#define	EXTI_EMR_EM15 EXTI_EMR_MR15

#define	EXTI_EMR_EM16 EXTI_EMR_MR16

#define	EXTI_EMR_EM17 EXTI_EMR_MR17

#define	EXTI_EMR_EM19 EXTI_EMR_MR19

#define	EXTI_EMR_EM20 EXTI_EMR_MR20

#define	EXTI_EMR_EM22 EXTI_EMR_MR22

#define	EXTI_EMR_EM23 EXTI_EMR_MR23

#define	EXTI_EMR_EM25 EXTI_EMR_MR25

#define	EXTI_EMR_EM30 EXTI_EMR_MR30

#define	EXTI_RTSR_TR0_Pos (0U)

#define	EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)

#define	EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk

#define	EXTI_RTSR_TR1_Pos (1U)

#define	EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)

#define	EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk

#define	EXTI_RTSR_TR2_Pos (2U)

#define	EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)

#define	EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk

#define	EXTI_RTSR_TR3_Pos (3U)

#define	EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)

#define	EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk

#define	EXTI_RTSR_TR4_Pos (4U)

#define	EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)

#define	EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk

#define	EXTI_RTSR_TR5_Pos (5U)

#define	EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)

#define	EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk

#define	EXTI_RTSR_TR6_Pos (6U)

#define	EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)

#define	EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk

#define	EXTI_RTSR_TR7_Pos (7U)

#define	EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)

#define	EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk

#define	EXTI_RTSR_TR8_Pos (8U)

#define	EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)

#define	EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk

#define	EXTI_RTSR_TR9_Pos (9U)

#define	EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)

#define	EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk

#define	EXTI_RTSR_TR10_Pos (10U)

#define	EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)

#define	EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk

#define	EXTI_RTSR_TR11_Pos (11U)

#define	EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)

#define	EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk

#define	EXTI_RTSR_TR12_Pos (12U)

#define	EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)

#define	EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk

#define	EXTI_RTSR_TR13_Pos (13U)

#define	EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)

#define	EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk

#define	EXTI_RTSR_TR14_Pos (14U)

#define	EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)

#define	EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk

#define	EXTI_RTSR_TR15_Pos (15U)

#define	EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)

#define	EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk

#define	EXTI_RTSR_TR16_Pos (16U)

#define	EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)

#define	EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk

#define	EXTI_RTSR_TR17_Pos (17U)

#define	EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)

#define	EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk

#define	EXTI_RTSR_TR19_Pos (19U)

#define	EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)

#define	EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk

#define	EXTI_RTSR_TR20_Pos (20U)

#define	EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)

#define	EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk

#define	EXTI_RTSR_TR22_Pos (22U)

#define	EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)

#define	EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk

#define	EXTI_RTSR_TR30_Pos (30U)

#define	EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos)

#define	EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk

#define	EXTI_RTSR_RT0 EXTI_RTSR_TR0

#define	EXTI_RTSR_RT1 EXTI_RTSR_TR1

#define	EXTI_RTSR_RT2 EXTI_RTSR_TR2

#define	EXTI_RTSR_RT3 EXTI_RTSR_TR3

#define	EXTI_RTSR_RT4 EXTI_RTSR_TR4

#define	EXTI_RTSR_RT5 EXTI_RTSR_TR5

#define	EXTI_RTSR_RT6 EXTI_RTSR_TR6

#define	EXTI_RTSR_RT7 EXTI_RTSR_TR7

#define	EXTI_RTSR_RT8 EXTI_RTSR_TR8

#define	EXTI_RTSR_RT9 EXTI_RTSR_TR9

#define	EXTI_RTSR_RT10 EXTI_RTSR_TR10

#define	EXTI_RTSR_RT11 EXTI_RTSR_TR11

#define	EXTI_RTSR_RT12 EXTI_RTSR_TR12

#define	EXTI_RTSR_RT13 EXTI_RTSR_TR13

#define	EXTI_RTSR_RT14 EXTI_RTSR_TR14

#define	EXTI_RTSR_RT15 EXTI_RTSR_TR15

#define	EXTI_RTSR_RT16 EXTI_RTSR_TR16

#define	EXTI_RTSR_RT17 EXTI_RTSR_TR17

#define	EXTI_RTSR_RT19 EXTI_RTSR_TR19

#define	EXTI_RTSR_RT20 EXTI_RTSR_TR20

#define	EXTI_RTSR_RT22 EXTI_RTSR_TR22

#define	EXTI_RTSR_RT30 EXTI_RTSR_TR30

#define	EXTI_FTSR_TR0_Pos (0U)

#define	EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)

#define	EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk

#define	EXTI_FTSR_TR1_Pos (1U)

#define	EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)

#define	EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk

#define	EXTI_FTSR_TR2_Pos (2U)

#define	EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)

#define	EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk

#define	EXTI_FTSR_TR3_Pos (3U)

#define	EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)

#define	EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk

#define	EXTI_FTSR_TR4_Pos (4U)

#define	EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)

#define	EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk

#define	EXTI_FTSR_TR5_Pos (5U)

#define	EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)

#define	EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk

#define	EXTI_FTSR_TR6_Pos (6U)

#define	EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)

#define	EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk

#define	EXTI_FTSR_TR7_Pos (7U)

#define	EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)

#define	EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk

#define	EXTI_FTSR_TR8_Pos (8U)

#define	EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)

#define	EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk

#define	EXTI_FTSR_TR9_Pos (9U)

#define	EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)

#define	EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk

#define	EXTI_FTSR_TR10_Pos (10U)

#define	EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)

#define	EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk

#define	EXTI_FTSR_TR11_Pos (11U)

#define	EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)

#define	EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk

#define	EXTI_FTSR_TR12_Pos (12U)

#define	EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)

#define	EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk

#define	EXTI_FTSR_TR13_Pos (13U)

#define	EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)

#define	EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk

#define	EXTI_FTSR_TR14_Pos (14U)

#define	EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)

#define	EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk

#define	EXTI_FTSR_TR15_Pos (15U)

#define	EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)

#define	EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk

#define	EXTI_FTSR_TR16_Pos (16U)

#define	EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)

#define	EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk

#define	EXTI_FTSR_TR17_Pos (17U)

#define	EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)

#define	EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk

#define	EXTI_FTSR_TR19_Pos (19U)

#define	EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)

#define	EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk

#define	EXTI_FTSR_TR20_Pos (20U)

#define	EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)

#define	EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk

#define	EXTI_FTSR_TR22_Pos (22U)

#define	EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)

#define	EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk

#define	EXTI_FTSR_TR30_Pos (30U)

#define	EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos)

#define	EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk

#define	EXTI_FTSR_FT0 EXTI_FTSR_TR0

#define	EXTI_FTSR_FT1 EXTI_FTSR_TR1

#define	EXTI_FTSR_FT2 EXTI_FTSR_TR2

#define	EXTI_FTSR_FT3 EXTI_FTSR_TR3

#define	EXTI_FTSR_FT4 EXTI_FTSR_TR4

#define	EXTI_FTSR_FT5 EXTI_FTSR_TR5

#define	EXTI_FTSR_FT6 EXTI_FTSR_TR6

#define	EXTI_FTSR_FT7 EXTI_FTSR_TR7

#define	EXTI_FTSR_FT8 EXTI_FTSR_TR8

#define	EXTI_FTSR_FT9 EXTI_FTSR_TR9

#define	EXTI_FTSR_FT10 EXTI_FTSR_TR10

#define	EXTI_FTSR_FT11 EXTI_FTSR_TR11

#define	EXTI_FTSR_FT12 EXTI_FTSR_TR12

#define	EXTI_FTSR_FT13 EXTI_FTSR_TR13

#define	EXTI_FTSR_FT14 EXTI_FTSR_TR14

#define	EXTI_FTSR_FT15 EXTI_FTSR_TR15

#define	EXTI_FTSR_FT16 EXTI_FTSR_TR16

#define	EXTI_FTSR_FT17 EXTI_FTSR_TR17

#define	EXTI_FTSR_FT19 EXTI_FTSR_TR19

#define	EXTI_FTSR_FT20 EXTI_FTSR_TR20

#define	EXTI_FTSR_FT22 EXTI_FTSR_TR22

#define	EXTI_FTSR_FT30 EXTI_FTSR_TR30

#define	EXTI_SWIER_SWIER0_Pos (0U)

#define	EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)

#define	EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk

#define	EXTI_SWIER_SWIER1_Pos (1U)

#define	EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)

#define	EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk

#define	EXTI_SWIER_SWIER2_Pos (2U)

#define	EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)

#define	EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk

#define	EXTI_SWIER_SWIER3_Pos (3U)

#define	EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)

#define	EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk

#define	EXTI_SWIER_SWIER4_Pos (4U)

#define	EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)

#define	EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk

#define	EXTI_SWIER_SWIER5_Pos (5U)

#define	EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)

#define	EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk

#define	EXTI_SWIER_SWIER6_Pos (6U)

#define	EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)

#define	EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk

#define	EXTI_SWIER_SWIER7_Pos (7U)

#define	EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)

#define	EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk

#define	EXTI_SWIER_SWIER8_Pos (8U)

#define	EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)

#define	EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk

#define	EXTI_SWIER_SWIER9_Pos (9U)

#define	EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)

#define	EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk

#define	EXTI_SWIER_SWIER10_Pos (10U)

#define	EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)

#define	EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk

#define	EXTI_SWIER_SWIER11_Pos (11U)

#define	EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)

#define	EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk

#define	EXTI_SWIER_SWIER12_Pos (12U)

#define	EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)

#define	EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk

#define	EXTI_SWIER_SWIER13_Pos (13U)

#define	EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)

#define	EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk

#define	EXTI_SWIER_SWIER14_Pos (14U)

#define	EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)

#define	EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk

#define	EXTI_SWIER_SWIER15_Pos (15U)

#define	EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)

#define	EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk

#define	EXTI_SWIER_SWIER16_Pos (16U)

#define	EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)

#define	EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk

#define	EXTI_SWIER_SWIER17_Pos (17U)

#define	EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)

#define	EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk

#define	EXTI_SWIER_SWIER19_Pos (19U)

#define	EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)

#define	EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk

#define	EXTI_SWIER_SWIER20_Pos (20U)

#define	EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)

#define	EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk

#define	EXTI_SWIER_SWIER22_Pos (22U)

#define	EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)

#define	EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk

#define	EXTI_SWIER_SWIER30_Pos (30U)

#define	EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos)

#define	EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk

#define	EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

#define	EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1

#define	EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2

#define	EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3

#define	EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4

#define	EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5

#define	EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6

#define	EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7

#define	EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8

#define	EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9

#define	EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10

#define	EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11

#define	EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12

#define	EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13

#define	EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14

#define	EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

#define	EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

#define	EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

#define	EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

#define	EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20

#define	EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22

#define	EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30

#define	EXTI_PR_PR0_Pos (0U)

#define	EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)

#define	EXTI_PR_PR0 EXTI_PR_PR0_Msk

#define	EXTI_PR_PR1_Pos (1U)

#define	EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)

#define	EXTI_PR_PR1 EXTI_PR_PR1_Msk

#define	EXTI_PR_PR2_Pos (2U)

#define	EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)

#define	EXTI_PR_PR2 EXTI_PR_PR2_Msk

#define	EXTI_PR_PR3_Pos (3U)

#define	EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)

#define	EXTI_PR_PR3 EXTI_PR_PR3_Msk

#define	EXTI_PR_PR4_Pos (4U)

#define	EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)

#define	EXTI_PR_PR4 EXTI_PR_PR4_Msk

#define	EXTI_PR_PR5_Pos (5U)

#define	EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)

#define	EXTI_PR_PR5 EXTI_PR_PR5_Msk

#define	EXTI_PR_PR6_Pos (6U)

#define	EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)

#define	EXTI_PR_PR6 EXTI_PR_PR6_Msk

#define	EXTI_PR_PR7_Pos (7U)

#define	EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)

#define	EXTI_PR_PR7 EXTI_PR_PR7_Msk

#define	EXTI_PR_PR8_Pos (8U)

#define	EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)

#define	EXTI_PR_PR8 EXTI_PR_PR8_Msk

#define	EXTI_PR_PR9_Pos (9U)

#define	EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)

#define	EXTI_PR_PR9 EXTI_PR_PR9_Msk

#define	EXTI_PR_PR10_Pos (10U)

#define	EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)

#define	EXTI_PR_PR10 EXTI_PR_PR10_Msk

#define	EXTI_PR_PR11_Pos (11U)

#define	EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)

#define	EXTI_PR_PR11 EXTI_PR_PR11_Msk

#define	EXTI_PR_PR12_Pos (12U)

#define	EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)

#define	EXTI_PR_PR12 EXTI_PR_PR12_Msk

#define	EXTI_PR_PR13_Pos (13U)

#define	EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)

#define	EXTI_PR_PR13 EXTI_PR_PR13_Msk

#define	EXTI_PR_PR14_Pos (14U)

#define	EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)

#define	EXTI_PR_PR14 EXTI_PR_PR14_Msk

#define	EXTI_PR_PR15_Pos (15U)

#define	EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)

#define	EXTI_PR_PR15 EXTI_PR_PR15_Msk

#define	EXTI_PR_PR16_Pos (16U)

#define	EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)

#define	EXTI_PR_PR16 EXTI_PR_PR16_Msk

#define	EXTI_PR_PR17_Pos (17U)

#define	EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)

#define	EXTI_PR_PR17 EXTI_PR_PR17_Msk

#define	EXTI_PR_PR19_Pos (19U)

#define	EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)

#define	EXTI_PR_PR19 EXTI_PR_PR19_Msk

#define	EXTI_PR_PR20_Pos (20U)

#define	EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)

#define	EXTI_PR_PR20 EXTI_PR_PR20_Msk

#define	EXTI_PR_PR22_Pos (22U)

#define	EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)

#define	EXTI_PR_PR22 EXTI_PR_PR22_Msk

#define	EXTI_PR_PR30_Pos (30U)

#define	EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos)

#define	EXTI_PR_PR30 EXTI_PR_PR30_Msk

#define	EXTI_PR_PIF0 EXTI_PR_PR0

#define	EXTI_PR_PIF1 EXTI_PR_PR1

#define	EXTI_PR_PIF2 EXTI_PR_PR2

#define	EXTI_PR_PIF3 EXTI_PR_PR3

#define	EXTI_PR_PIF4 EXTI_PR_PR4

#define	EXTI_PR_PIF5 EXTI_PR_PR5

#define	EXTI_PR_PIF6 EXTI_PR_PR6

#define	EXTI_PR_PIF6 EXTI_PR_PR6

#define	EXTI_PR_PIF7 EXTI_PR_PR7

#define	EXTI_PR_PIF8 EXTI_PR_PR8

#define	EXTI_PR_PIF9 EXTI_PR_PR9

#define	EXTI_PR_PIF10 EXTI_PR_PR10

#define	EXTI_PR_PIF11 EXTI_PR_PR11

#define	EXTI_PR_PIF12 EXTI_PR_PR12

#define	EXTI_PR_PIF13 EXTI_PR_PR13

#define	EXTI_PR_PIF14 EXTI_PR_PR14

#define	EXTI_PR_PIF15 EXTI_PR_PR15

#define	EXTI_PR_PIF16 EXTI_PR_PR16

#define	EXTI_PR_PIF17 EXTI_PR_PR17

#define	EXTI_PR_PIF19 EXTI_PR_PR19

#define	EXTI_PR_PIF20 EXTI_PR_PR20

#define	EXTI_PR_PIF22 EXTI_PR_PR22

#define	EXTI_PR_PIF30 EXTI_PR_PR30

#define	EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */

#define	EXTI_IMR2_MR32_Pos (0U)

#define	EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos)

#define	EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk

#define	EXTI_IMR2_IM32 EXTI_IMR2_MR32

#define	EXTI_IMR2_IM_Pos (0U)

#define	EXTI_IMR2_IM_Msk (0x1UL << EXTI_IMR2_IM_Pos)

#define	EXTI_IMR2_IM EXTI_IMR2_IM_Msk

#define	EXTI_EMR2_MR32_Pos (0U)

#define	EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos)

#define	EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk

#define	EXTI_EMR2_EM32 EXTI_EMR2_MR32

#define	EXTI_EMR2_EM_Pos (0U)

#define	EXTI_EMR2_EM_Msk (0x1UL << EXTI_EMR2_EM_Pos)

#define	EXTI_EMR2_EM EXTI_EMR2_EM_Msk

#define	EXTI_RTSR2_TR32_Pos (0U)

#define	EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos)

#define	EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk

#define	EXTI_RTSR2_RT32 EXTI_RTSR2_TR32

#define	EXTI_FTSR2_TR32_Pos (0U)

#define	EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos)

#define	EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk

#define	EXTI_FTSR2_FT32 EXTI_FTSR2_TR32

#define	EXTI_SWIER2_SWIER32_Pos (0U)

#define	EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos)

#define	EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk

#define	EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32

#define	EXTI_PR2_PR32_Pos (0U)

#define	EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos)

#define	EXTI_PR2_PR32 EXTI_PR2_PR32_Msk

#define	EXTI_PR2_PIF32 EXTI_PR2_PR32

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_HLFCYA_Pos (3U)

#define	FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)

#define	FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk

#define	FLASH_ACR_PRFTBE_Pos (4U)

#define	FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)

#define	FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk

#define	FLASH_ACR_PRFTBS_Pos (5U)

#define	FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)

#define	FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk

#define	FLASH_KEYR_FKEYR_Pos (0U)

#define	FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)

#define	FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk

#define	RDP_KEY_Pos (0U)

#define	RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)

#define	RDP_KEY RDP_KEY_Msk

#define	FLASH_KEY1_Pos (0U)

#define	FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)

#define	FLASH_KEY1 FLASH_KEY1_Msk

#define	FLASH_KEY2_Pos (0U)

#define	FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)

#define	FLASH_KEY2 FLASH_KEY2_Msk

#define	FLASH_OPTKEYR_OPTKEYR_Pos (0U)

#define	FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)

#define	FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk

#define	FLASH_OPTKEY1 FLASH_KEY1

#define	FLASH_OPTKEY2 FLASH_KEY2

#define	FLASH_SR_BSY_Pos (0U)

#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

#define	FLASH_SR_BSY FLASH_SR_BSY_Msk

#define	FLASH_SR_PGERR_Pos (2U)

#define	FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)

#define	FLASH_SR_PGERR FLASH_SR_PGERR_Msk

#define	FLASH_SR_WRPERR_Pos (4U)

#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

#define	FLASH_SR_EOP_Pos (5U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER_Pos (2U)

#define	FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

#define	FLASH_CR_MER FLASH_CR_MER_Msk

#define	FLASH_CR_OPTPG_Pos (4U)

#define	FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)

#define	FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk

#define	FLASH_CR_OPTER_Pos (5U)

#define	FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)

#define	FLASH_CR_OPTER FLASH_CR_OPTER_Msk

#define	FLASH_CR_STRT_Pos (6U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_LOCK_Pos (7U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_CR_OPTWRE_Pos (9U)

#define	FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)

#define	FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk

#define	FLASH_CR_ERRIE_Pos (10U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_EOPIE_Pos (12U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_CR_OBL_LAUNCH_Pos (13U)

#define	FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

#define	FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

#define	FLASH_AR_FAR_Pos (0U)

#define	FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)

#define	FLASH_AR_FAR FLASH_AR_FAR_Msk

#define	FLASH_OBR_OPTERR_Pos (0U)

#define	FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)

#define	FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk

#define	FLASH_OBR_RDPRT_Pos (1U)

#define	FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk

#define	FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_USER_Pos (8U)

#define	FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos)

#define	FLASH_OBR_USER FLASH_OBR_USER_Msk

#define	FLASH_OBR_IWDG_SW_Pos (8U)

#define	FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)

#define	FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk

#define	FLASH_OBR_nRST_STOP_Pos (9U)

#define	FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)

#define	FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk

#define	FLASH_OBR_nRST_STDBY_Pos (10U)

#define	FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)

#define	FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk

#define	FLASH_OBR_nBOOT1_Pos (12U)

#define	FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos)

#define	FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk

#define	FLASH_OBR_VDDA_MONITOR_Pos (13U)

#define	FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos)

#define	FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk

#define	FLASH_OBR_SRAM_PE_Pos (14U)

#define	FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos)

#define	FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk

#define	FLASH_OBR_DATA0_Pos (16U)

#define	FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)

#define	FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk

#define	FLASH_OBR_DATA1_Pos (24U)

#define	FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)

#define	FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk

#define	FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW

#define	FLASH_WRPR_WRP_Pos (0U)

#define	FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)

#define	FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk

#define	OB_RDP_RDP_Pos (0U)

#define	OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos)

#define	OB_RDP_RDP OB_RDP_RDP_Msk

#define	OB_RDP_nRDP_Pos (8U)

#define	OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos)

#define	OB_RDP_nRDP OB_RDP_nRDP_Msk

#define	OB_USER_USER_Pos (16U)

#define	OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos)

#define	OB_USER_USER OB_USER_USER_Msk

#define	OB_USER_nUSER_Pos (24U)

#define	OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos)

#define	OB_USER_nUSER OB_USER_nUSER_Msk

#define	OB_WRP0_WRP0_Pos (0U)

#define	OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos)

#define	OB_WRP0_WRP0 OB_WRP0_WRP0_Msk

#define	OB_WRP0_nWRP0_Pos (8U)

#define	OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos)

#define	OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk

#define	OB_WRP1_WRP1_Pos (16U)

#define	OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos)

#define	OB_WRP1_WRP1 OB_WRP1_WRP1_Msk

#define	OB_WRP1_nWRP1_Pos (24U)

#define	OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos)

#define	OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk

#define	GPIO_MODER_MODER0_Pos (0U)

#define	GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk

#define	GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER1_Pos (2U)

#define	GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk

#define	GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER2_Pos (4U)

#define	GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk

#define	GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER3_Pos (6U)

#define	GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk

#define	GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER4_Pos (8U)

#define	GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk

#define	GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER5_Pos (10U)

#define	GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk

#define	GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER6_Pos (12U)

#define	GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk

#define	GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER7_Pos (14U)

#define	GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk

#define	GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER8_Pos (16U)

#define	GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk

#define	GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER9_Pos (18U)

#define	GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk

#define	GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER10_Pos (20U)

#define	GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk

#define	GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER11_Pos (22U)

#define	GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk

#define	GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER12_Pos (24U)

#define	GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk

#define	GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER13_Pos (26U)

#define	GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk

#define	GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER14_Pos (28U)

#define	GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk

#define	GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER15_Pos (30U)

#define	GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk

#define	GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_OTYPER_OT_0 (0x00000001U)

#define	GPIO_OTYPER_OT_1 (0x00000002U)

#define	GPIO_OTYPER_OT_2 (0x00000004U)

#define	GPIO_OTYPER_OT_3 (0x00000008U)

#define	GPIO_OTYPER_OT_4 (0x00000010U)

#define	GPIO_OTYPER_OT_5 (0x00000020U)

#define	GPIO_OTYPER_OT_6 (0x00000040U)

#define	GPIO_OTYPER_OT_7 (0x00000080U)

#define	GPIO_OTYPER_OT_8 (0x00000100U)

#define	GPIO_OTYPER_OT_9 (0x00000200U)

#define	GPIO_OTYPER_OT_10 (0x00000400U)

#define	GPIO_OTYPER_OT_11 (0x00000800U)

#define	GPIO_OTYPER_OT_12 (0x00001000U)

#define	GPIO_OTYPER_OT_13 (0x00002000U)

#define	GPIO_OTYPER_OT_14 (0x00004000U)

#define	GPIO_OTYPER_OT_15 (0x00008000U)

#define	GPIO_OSPEEDER_OSPEEDR0_Pos (0U)

#define	GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk

#define	GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1_Pos (2U)

#define	GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk

#define	GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2_Pos (4U)

#define	GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk

#define	GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3_Pos (6U)

#define	GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk

#define	GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4_Pos (8U)

#define	GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk

#define	GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5_Pos (10U)

#define	GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk

#define	GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6_Pos (12U)

#define	GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk

#define	GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7_Pos (14U)

#define	GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk

#define	GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8_Pos (16U)

#define	GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk

#define	GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9_Pos (18U)

#define	GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk

#define	GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10_Pos (20U)

#define	GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk

#define	GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11_Pos (22U)

#define	GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk

#define	GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12_Pos (24U)

#define	GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk

#define	GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13_Pos (26U)

#define	GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk

#define	GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14_Pos (28U)

#define	GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk

#define	GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15_Pos (30U)

#define	GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk

#define	GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_PUPDR_PUPDR0_Pos (0U)

#define	GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk

#define	GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR1_Pos (2U)

#define	GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk

#define	GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR2_Pos (4U)

#define	GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk

#define	GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR3_Pos (6U)

#define	GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk

#define	GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR4_Pos (8U)

#define	GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk

#define	GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR5_Pos (10U)

#define	GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk

#define	GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR6_Pos (12U)

#define	GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk

#define	GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR7_Pos (14U)

#define	GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk

#define	GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR8_Pos (16U)

#define	GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk

#define	GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR9_Pos (18U)

#define	GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk

#define	GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR10_Pos (20U)

#define	GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk

#define	GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR11_Pos (22U)

#define	GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk

#define	GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR12_Pos (24U)

#define	GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk

#define	GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR13_Pos (26U)

#define	GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk

#define	GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR14_Pos (28U)

#define	GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk

#define	GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR15_Pos (30U)

#define	GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk

#define	GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_IDR_0 (0x00000001U)

#define	GPIO_IDR_1 (0x00000002U)

#define	GPIO_IDR_2 (0x00000004U)

#define	GPIO_IDR_3 (0x00000008U)

#define	GPIO_IDR_4 (0x00000010U)

#define	GPIO_IDR_5 (0x00000020U)

#define	GPIO_IDR_6 (0x00000040U)

#define	GPIO_IDR_7 (0x00000080U)

#define	GPIO_IDR_8 (0x00000100U)

#define	GPIO_IDR_9 (0x00000200U)

#define	GPIO_IDR_10 (0x00000400U)

#define	GPIO_IDR_11 (0x00000800U)

#define	GPIO_IDR_12 (0x00001000U)

#define	GPIO_IDR_13 (0x00002000U)

#define	GPIO_IDR_14 (0x00004000U)

#define	GPIO_IDR_15 (0x00008000U)

#define	GPIO_ODR_0 (0x00000001U)

#define	GPIO_ODR_1 (0x00000002U)

#define	GPIO_ODR_2 (0x00000004U)

#define	GPIO_ODR_3 (0x00000008U)

#define	GPIO_ODR_4 (0x00000010U)

#define	GPIO_ODR_5 (0x00000020U)

#define	GPIO_ODR_6 (0x00000040U)

#define	GPIO_ODR_7 (0x00000080U)

#define	GPIO_ODR_8 (0x00000100U)

#define	GPIO_ODR_9 (0x00000200U)

#define	GPIO_ODR_10 (0x00000400U)

#define	GPIO_ODR_11 (0x00000800U)

#define	GPIO_ODR_12 (0x00001000U)

#define	GPIO_ODR_13 (0x00002000U)

#define	GPIO_ODR_14 (0x00004000U)

#define	GPIO_ODR_15 (0x00008000U)

#define	GPIO_BSRR_BS_0 (0x00000001U)

#define	GPIO_BSRR_BS_1 (0x00000002U)

#define	GPIO_BSRR_BS_2 (0x00000004U)

#define	GPIO_BSRR_BS_3 (0x00000008U)

#define	GPIO_BSRR_BS_4 (0x00000010U)

#define	GPIO_BSRR_BS_5 (0x00000020U)

#define	GPIO_BSRR_BS_6 (0x00000040U)

#define	GPIO_BSRR_BS_7 (0x00000080U)

#define	GPIO_BSRR_BS_8 (0x00000100U)

#define	GPIO_BSRR_BS_9 (0x00000200U)

#define	GPIO_BSRR_BS_10 (0x00000400U)

#define	GPIO_BSRR_BS_11 (0x00000800U)

#define	GPIO_BSRR_BS_12 (0x00001000U)

#define	GPIO_BSRR_BS_13 (0x00002000U)

#define	GPIO_BSRR_BS_14 (0x00004000U)

#define	GPIO_BSRR_BS_15 (0x00008000U)

#define	GPIO_BSRR_BR_0 (0x00010000U)

#define	GPIO_BSRR_BR_1 (0x00020000U)

#define	GPIO_BSRR_BR_2 (0x00040000U)

#define	GPIO_BSRR_BR_3 (0x00080000U)

#define	GPIO_BSRR_BR_4 (0x00100000U)

#define	GPIO_BSRR_BR_5 (0x00200000U)

#define	GPIO_BSRR_BR_6 (0x00400000U)

#define	GPIO_BSRR_BR_7 (0x00800000U)

#define	GPIO_BSRR_BR_8 (0x01000000U)

#define	GPIO_BSRR_BR_9 (0x02000000U)

#define	GPIO_BSRR_BR_10 (0x04000000U)

#define	GPIO_BSRR_BR_11 (0x08000000U)

#define	GPIO_BSRR_BR_12 (0x10000000U)

#define	GPIO_BSRR_BR_13 (0x20000000U)

#define	GPIO_BSRR_BR_14 (0x40000000U)

#define	GPIO_BSRR_BR_15 (0x80000000U)

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	GPIO_AFRL_AFRL0_Pos (0U)

#define	GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)

#define	GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk

#define	GPIO_AFRL_AFRL1_Pos (4U)

#define	GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)

#define	GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk

#define	GPIO_AFRL_AFRL2_Pos (8U)

#define	GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)

#define	GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk

#define	GPIO_AFRL_AFRL3_Pos (12U)

#define	GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)

#define	GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk

#define	GPIO_AFRL_AFRL4_Pos (16U)

#define	GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)

#define	GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk

#define	GPIO_AFRL_AFRL5_Pos (20U)

#define	GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)

#define	GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk

#define	GPIO_AFRL_AFRL6_Pos (24U)

#define	GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)

#define	GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk

#define	GPIO_AFRL_AFRL7_Pos (28U)

#define	GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)

#define	GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk

#define	GPIO_AFRH_AFRH0_Pos (0U)

#define	GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)

#define	GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk

#define	GPIO_AFRH_AFRH1_Pos (4U)

#define	GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)

#define	GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk

#define	GPIO_AFRH_AFRH2_Pos (8U)

#define	GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)

#define	GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk

#define	GPIO_AFRH_AFRH3_Pos (12U)

#define	GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)

#define	GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk

#define	GPIO_AFRH_AFRH4_Pos (16U)

#define	GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)

#define	GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk

#define	GPIO_AFRH_AFRH5_Pos (20U)

#define	GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)

#define	GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk

#define	GPIO_AFRH_AFRH6_Pos (24U)

#define	GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)

#define	GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk

#define	GPIO_AFRH_AFRH7_Pos (28U)

#define	GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)

#define	GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk

#define	GPIO_BRR_BR_0 (0x00000001U)

#define	GPIO_BRR_BR_1 (0x00000002U)

#define	GPIO_BRR_BR_2 (0x00000004U)

#define	GPIO_BRR_BR_3 (0x00000008U)

#define	GPIO_BRR_BR_4 (0x00000010U)

#define	GPIO_BRR_BR_5 (0x00000020U)

#define	GPIO_BRR_BR_6 (0x00000040U)

#define	GPIO_BRR_BR_7 (0x00000080U)

#define	GPIO_BRR_BR_8 (0x00000100U)

#define	GPIO_BRR_BR_9 (0x00000200U)

#define	GPIO_BRR_BR_10 (0x00000400U)

#define	GPIO_BRR_BR_11 (0x00000800U)

#define	GPIO_BRR_BR_12 (0x00001000U)

#define	GPIO_BRR_BR_13 (0x00002000U)

#define	GPIO_BRR_BR_14 (0x00004000U)

#define	GPIO_BRR_BR_15 (0x00008000U)

#define	HRTIM_MCR_CK_PSC_Pos (0U)

#define	HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos)

#define	HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk

#define	HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos)

#define	HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos)

#define	HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos)

#define	HRTIM_MCR_CONT_Pos (3U)

#define	HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos)

#define	HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk

#define	HRTIM_MCR_RETRIG_Pos (4U)

#define	HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos)

#define	HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk

#define	HRTIM_MCR_HALF_Pos (5U)

#define	HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos)

#define	HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk

#define	HRTIM_MCR_SYNC_IN_Pos (8U)

#define	HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos)

#define	HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk

#define	HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos)

#define	HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos)

#define	HRTIM_MCR_SYNCRSTM_Pos (10U)

#define	HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)

#define	HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk

#define	HRTIM_MCR_SYNCSTRTM_Pos (11U)

#define	HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)

#define	HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk

#define	HRTIM_MCR_SYNC_OUT_Pos (12U)

#define	HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)

#define	HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk

#define	HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)

#define	HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)

#define	HRTIM_MCR_SYNC_SRC_Pos (14U)

#define	HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)

#define	HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk

#define	HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)

#define	HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)

#define	HRTIM_MCR_MCEN_Pos (16U)

#define	HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos)

#define	HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk

#define	HRTIM_MCR_TACEN_Pos (17U)

#define	HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos)

#define	HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk

#define	HRTIM_MCR_TBCEN_Pos (18U)

#define	HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos)

#define	HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk

#define	HRTIM_MCR_TCCEN_Pos (19U)

#define	HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos)

#define	HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk

#define	HRTIM_MCR_TDCEN_Pos (20U)

#define	HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos)

#define	HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk

#define	HRTIM_MCR_TECEN_Pos (21U)

#define	HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos)

#define	HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk

#define	HRTIM_MCR_DACSYNC_Pos (25U)

#define	HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos)

#define	HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk

#define	HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos)

#define	HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos)

#define	HRTIM_MCR_PREEN_Pos (27U)

#define	HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos)

#define	HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk

#define	HRTIM_MCR_MREPU_Pos (29U)

#define	HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos)

#define	HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk

#define	HRTIM_MCR_BRSTDMA_Pos (30U)

#define	HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos)

#define	HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk

#define	HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos)

#define	HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos)

#define	HRTIM_MISR_MCMP1_Pos (0U)

#define	HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos)

#define	HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk

#define	HRTIM_MISR_MCMP2_Pos (1U)

#define	HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos)

#define	HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk

#define	HRTIM_MISR_MCMP3_Pos (2U)

#define	HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos)

#define	HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk

#define	HRTIM_MISR_MCMP4_Pos (3U)

#define	HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos)

#define	HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk

#define	HRTIM_MISR_MREP_Pos (4U)

#define	HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos)

#define	HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk

#define	HRTIM_MISR_SYNC_Pos (5U)

#define	HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos)

#define	HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk

#define	HRTIM_MISR_MUPD_Pos (6U)

#define	HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos)

#define	HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk

#define	HRTIM_MICR_MCMP1_Pos (0U)

#define	HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos)

#define	HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk

#define	HRTIM_MICR_MCMP2_Pos (1U)

#define	HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos)

#define	HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk

#define	HRTIM_MICR_MCMP3_Pos (2U)

#define	HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos)

#define	HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk

#define	HRTIM_MICR_MCMP4_Pos (3U)

#define	HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos)

#define	HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk

#define	HRTIM_MICR_MREP_Pos (4U)

#define	HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos)

#define	HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk

#define	HRTIM_MICR_SYNC_Pos (5U)

#define	HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos)

#define	HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk

#define	HRTIM_MICR_MUPD_Pos (6U)

#define	HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos)

#define	HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk

#define	HRTIM_MDIER_MCMP1IE_Pos (0U)

#define	HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)

#define	HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk

#define	HRTIM_MDIER_MCMP2IE_Pos (1U)

#define	HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)

#define	HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk

#define	HRTIM_MDIER_MCMP3IE_Pos (2U)

#define	HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)

#define	HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk

#define	HRTIM_MDIER_MCMP4IE_Pos (3U)

#define	HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)

#define	HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk

#define	HRTIM_MDIER_MREPIE_Pos (4U)

#define	HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos)

#define	HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk

#define	HRTIM_MDIER_SYNCIE_Pos (5U)

#define	HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos)

#define	HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk

#define	HRTIM_MDIER_MUPDIE_Pos (6U)

#define	HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos)

#define	HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk

#define	HRTIM_MDIER_MCMP1DE_Pos (16U)

#define	HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)

#define	HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk

#define	HRTIM_MDIER_MCMP2DE_Pos (17U)

#define	HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)

#define	HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk

#define	HRTIM_MDIER_MCMP3DE_Pos (18U)

#define	HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)

#define	HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk

#define	HRTIM_MDIER_MCMP4DE_Pos (19U)

#define	HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)

#define	HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk

#define	HRTIM_MDIER_MREPDE_Pos (20U)

#define	HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos)

#define	HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk

#define	HRTIM_MDIER_SYNCDE_Pos (21U)

#define	HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos)

#define	HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk

#define	HRTIM_MDIER_MUPDDE_Pos (22U)

#define	HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos)

#define	HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk

#define	HRTIM_MCNTR_MCNTR_Pos (0U)

#define	HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)

#define	HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk

#define	HRTIM_MPER_MPER_Pos (0U)

#define	HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos)

#define	HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk

#define	HRTIM_MREP_MREP_Pos (0U)

#define	HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos)

#define	HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk

#define	HRTIM_MCMP1R_MCMP1R_Pos (0U)

#define	HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)

#define	HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk

#define	HRTIM_MCMP2R_MCMP2R_Pos (0U)

#define	HRTIM_MCMP2R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)

#define	HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk

#define	HRTIM_MCMP3R_MCMP3R_Pos (0U)

#define	HRTIM_MCMP3R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)

#define	HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk

#define	HRTIM_MCMP4R_MCMP4R_Pos (0U)

#define	HRTIM_MCMP4R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)

#define	HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk

#define	HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R

#define	HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R

#define	HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R

#define	HRTIM_TIMCR_CK_PSC_Pos (0U)

#define	HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)

#define	HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk

#define	HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)

#define	HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)

#define	HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)

#define	HRTIM_TIMCR_CONT_Pos (3U)

#define	HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos)

#define	HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk

#define	HRTIM_TIMCR_RETRIG_Pos (4U)

#define	HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos)

#define	HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk

#define	HRTIM_TIMCR_HALF_Pos (5U)

#define	HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos)

#define	HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk

#define	HRTIM_TIMCR_PSHPLL_Pos (6U)

#define	HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)

#define	HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk

#define	HRTIM_TIMCR_SYNCRST_Pos (10U)

#define	HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)

#define	HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk

#define	HRTIM_TIMCR_SYNCSTRT_Pos (11U)

#define	HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)

#define	HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk

#define	HRTIM_TIMCR_DELCMP2_Pos (12U)

#define	HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)

#define	HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk

#define	HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)

#define	HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)

#define	HRTIM_TIMCR_DELCMP4_Pos (14U)

#define	HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)

#define	HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk

#define	HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)

#define	HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)

#define	HRTIM_TIMCR_TREPU_Pos (17U)

#define	HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos)

#define	HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk

#define	HRTIM_TIMCR_TRSTU_Pos (18U)

#define	HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos)

#define	HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk

#define	HRTIM_TIMCR_TAU_Pos (19U)

#define	HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos)

#define	HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk

#define	HRTIM_TIMCR_TBU_Pos (20U)

#define	HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos)

#define	HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk

#define	HRTIM_TIMCR_TCU_Pos (21U)

#define	HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos)

#define	HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk

#define	HRTIM_TIMCR_TDU_Pos (22U)

#define	HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos)

#define	HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk

#define	HRTIM_TIMCR_TEU_Pos (23U)

#define	HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos)

#define	HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk

#define	HRTIM_TIMCR_MSTU_Pos (24U)

#define	HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos)

#define	HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk

#define	HRTIM_TIMCR_DACSYNC_Pos (25U)

#define	HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)

#define	HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk

#define	HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)

#define	HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)

#define	HRTIM_TIMCR_PREEN_Pos (27U)

#define	HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos)

#define	HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk

#define	HRTIM_TIMCR_UPDGAT_Pos (28U)

#define	HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)

#define	HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk

#define	HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)

#define	HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)

#define	HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)

#define	HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)

#define	HRTIM_TIMICR_DLYPRT1C_Pos HRTIM_TIMICR_RSTC_Pos

#define	HRTIM_TIMICR_DLYPRT1C_Msk HRTIM_TIMICR_DLYPRTC_Msk

#define	HRTIM_TIMICR_DLYPRT1C HRTIM_TIMICR_DLYPRTC

#define	HRTIM_TIMICR_DLYPRT2C_Pos HRTIM_TIMICR_RSTC_Pos

#define	HRTIM_TIMICR_DLYPRT2C_Msk HRTIM_TIMICR_DLYPRTC_Msk

#define	HRTIM_TIMICR_DLYPRT2C HRTIM_TIMICR_DLYPRTC

#define	HRTIM_TIMISR_CMP1_Pos (0U)

#define	HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos)

#define	HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk

#define	HRTIM_TIMISR_CMP2_Pos (1U)

#define	HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos)

#define	HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk

#define	HRTIM_TIMISR_CMP3_Pos (2U)

#define	HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos)

#define	HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk

#define	HRTIM_TIMISR_CMP4_Pos (3U)

#define	HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos)

#define	HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk

#define	HRTIM_TIMISR_REP_Pos (4U)

#define	HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos)

#define	HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk

#define	HRTIM_TIMISR_UPD_Pos (6U)

#define	HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos)

#define	HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk

#define	HRTIM_TIMISR_CPT1_Pos (7U)

#define	HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos)

#define	HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk

#define	HRTIM_TIMISR_CPT2_Pos (8U)

#define	HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos)

#define	HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk

#define	HRTIM_TIMISR_SET1_Pos (9U)

#define	HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos)

#define	HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk

#define	HRTIM_TIMISR_RST1_Pos (10U)

#define	HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos)

#define	HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk

#define	HRTIM_TIMISR_SET2_Pos (11U)

#define	HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos)

#define	HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk

#define	HRTIM_TIMISR_RST2_Pos (12U)

#define	HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos)

#define	HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk

#define	HRTIM_TIMISR_RST_Pos (13U)

#define	HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos)

#define	HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk

#define	HRTIM_TIMISR_DLYPRT_Pos (14U)

#define	HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)

#define	HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk

#define	HRTIM_TIMISR_CPPSTAT_Pos (16U)

#define	HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)

#define	HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk

#define	HRTIM_TIMISR_IPPSTAT_Pos (17U)

#define	HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)

#define	HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk

#define	HRTIM_TIMISR_O1STAT_Pos (18U)

#define	HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos)

#define	HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk

#define	HRTIM_TIMISR_O2STAT_Pos (19U)

#define	HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos)

#define	HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk

#define	HRTIM_TIMISR_O1CPY_Pos (20U)

#define	HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos)

#define	HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk

#define	HRTIM_TIMISR_O2CPY_Pos (21U)

#define	HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos)

#define	HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk

#define	HRTIM_TIMICR_CMP1C_Pos (0U)

#define	HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos)

#define	HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk

#define	HRTIM_TIMICR_CMP2C_Pos (1U)

#define	HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos)

#define	HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk

#define	HRTIM_TIMICR_CMP3C_Pos (2U)

#define	HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos)

#define	HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk

#define	HRTIM_TIMICR_CMP4C_Pos (3U)

#define	HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos)

#define	HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk

#define	HRTIM_TIMICR_REPC_Pos (4U)

#define	HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos)

#define	HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk

#define	HRTIM_TIMICR_UPDC_Pos (6U)

#define	HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos)

#define	HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk

#define	HRTIM_TIMICR_CPT1C_Pos (7U)

#define	HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos)

#define	HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk

#define	HRTIM_TIMICR_CPT2C_Pos (8U)

#define	HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos)

#define	HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk

#define	HRTIM_TIMICR_SET1C_Pos (9U)

#define	HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos)

#define	HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk

#define	HRTIM_TIMICR_RST1C_Pos (10U)

#define	HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos)

#define	HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk

#define	HRTIM_TIMICR_SET2C_Pos (11U)

#define	HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos)

#define	HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk

#define	HRTIM_TIMICR_RST2C_Pos (12U)

#define	HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos)

#define	HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk

#define	HRTIM_TIMICR_RSTC_Pos (13U)

#define	HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos)

#define	HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk

#define	HRTIM_TIMICR_DLYPRTC_Pos (14U)

#define	HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)

#define	HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk

#define	HRTIM_TIMDIER_CMP1IE_Pos (0U)

#define	HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)

#define	HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk

#define	HRTIM_TIMDIER_CMP2IE_Pos (1U)

#define	HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)

#define	HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk

#define	HRTIM_TIMDIER_CMP3IE_Pos (2U)

#define	HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)

#define	HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk

#define	HRTIM_TIMDIER_CMP4IE_Pos (3U)

#define	HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)

#define	HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk

#define	HRTIM_TIMDIER_REPIE_Pos (4U)

#define	HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos)

#define	HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk

#define	HRTIM_TIMDIER_UPDIE_Pos (6U)

#define	HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)

#define	HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk

#define	HRTIM_TIMDIER_CPT1IE_Pos (7U)

#define	HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)

#define	HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk

#define	HRTIM_TIMDIER_CPT2IE_Pos (8U)

#define	HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)

#define	HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk

#define	HRTIM_TIMDIER_SET1IE_Pos (9U)

#define	HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)

#define	HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk

#define	HRTIM_TIMDIER_RST1IE_Pos (10U)

#define	HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)

#define	HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk

#define	HRTIM_TIMDIER_SET2IE_Pos (11U)

#define	HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)

#define	HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk

#define	HRTIM_TIMDIER_RST2IE_Pos (12U)

#define	HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)

#define	HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk

#define	HRTIM_TIMDIER_RSTIE_Pos (13U)

#define	HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)

#define	HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk

#define	HRTIM_TIMDIER_DLYPRTIE_Pos (14U)

#define	HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)

#define	HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk

#define	HRTIM_TIMDIER_CMP1DE_Pos (16U)

#define	HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)

#define	HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk

#define	HRTIM_TIMDIER_CMP2DE_Pos (17U)

#define	HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)

#define	HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk

#define	HRTIM_TIMDIER_CMP3DE_Pos (18U)

#define	HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)

#define	HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk

#define	HRTIM_TIMDIER_CMP4DE_Pos (19U)

#define	HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)

#define	HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk

#define	HRTIM_TIMDIER_REPDE_Pos (20U)

#define	HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos)

#define	HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk

#define	HRTIM_TIMDIER_UPDDE_Pos (22U)

#define	HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)

#define	HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk

#define	HRTIM_TIMDIER_CPT1DE_Pos (23U)

#define	HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)

#define	HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk

#define	HRTIM_TIMDIER_CPT2DE_Pos (24U)

#define	HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)

#define	HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk

#define	HRTIM_TIMDIER_SET1DE_Pos (25U)

#define	HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)

#define	HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk

#define	HRTIM_TIMDIER_RST1DE_Pos (26U)

#define	HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)

#define	HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk

#define	HRTIM_TIMDIER_SET2DE_Pos (27U)

#define	HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)

#define	HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk

#define	HRTIM_TIMDIER_RST2DE_Pos (28U)

#define	HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)

#define	HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk

#define	HRTIM_TIMDIER_RSTDE_Pos (29U)

#define	HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)

#define	HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk

#define	HRTIM_TIMDIER_DLYPRTDE_Pos (30U)

#define	HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)

#define	HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk

#define	HRTIM_CNTR_CNTR_Pos (0U)

#define	HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)

#define	HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk

#define	HRTIM_PER_PER_Pos (0U)

#define	HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos)

#define	HRTIM_PER_PER HRTIM_PER_PER_Msk

#define	HRTIM_REP_REP_Pos (0U)

#define	HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos)

#define	HRTIM_REP_REP HRTIM_REP_REP_Msk

#define	HRTIM_CMP1R_CMP1R_Pos (0U)

#define	HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)

#define	HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk

#define	HRTIM_CMP1CR_CMP1CR_Pos (0U)

#define	HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)

#define	HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk

#define	HRTIM_CMP2R_CMP2R_Pos (0U)

#define	HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)

#define	HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk

#define	HRTIM_CMP3R_CMP3R_Pos (0U)

#define	HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)

#define	HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk

#define	HRTIM_CMP4R_CMP4R_Pos (0U)

#define	HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)

#define	HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk

#define	HRTIM_CPT1R_CPT1R_Pos (0U)

#define	HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)

#define	HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk

#define	HRTIM_CPT2R_CPT2R_Pos (0U)

#define	HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)

#define	HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk

#define	HRTIM_DTR_DTR_Pos (0U)

#define	HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk

#define	HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos)

#define	HRTIM_DTR_SDTR_Pos (9U)

#define	HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos)

#define	HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk

#define	HRTIM_DTR_DTPRSC_Pos (10U)

#define	HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos)

#define	HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk

#define	HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos)

#define	HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos)

#define	HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos)

#define	HRTIM_DTR_DTRSLK_Pos (14U)

#define	HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos)

#define	HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk

#define	HRTIM_DTR_DTRLK_Pos (15U)

#define	HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos)

#define	HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk

#define	HRTIM_DTR_DTF_Pos (16U)

#define	HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk

#define	HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos)

#define	HRTIM_DTR_SDTF_Pos (25U)

#define	HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos)

#define	HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk

#define	HRTIM_DTR_DTFSLK_Pos (30U)

#define	HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos)

#define	HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk

#define	HRTIM_DTR_DTFLK_Pos (31U)

#define	HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos)

#define	HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk

#define	HRTIM_SET1R_SST_Pos (0U)

#define	HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos)

#define	HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk

#define	HRTIM_SET1R_RESYNC_Pos (1U)

#define	HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos)

#define	HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk

#define	HRTIM_SET1R_PER_Pos (2U)

#define	HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos)

#define	HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk

#define	HRTIM_SET1R_CMP1_Pos (3U)

#define	HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos)

#define	HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk

#define	HRTIM_SET1R_CMP2_Pos (4U)

#define	HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos)

#define	HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk

#define	HRTIM_SET1R_CMP3_Pos (5U)

#define	HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos)

#define	HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk

#define	HRTIM_SET1R_CMP4_Pos (6U)

#define	HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos)

#define	HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk

#define	HRTIM_SET1R_MSTPER_Pos (7U)

#define	HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos)

#define	HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk

#define	HRTIM_SET1R_MSTCMP1_Pos (8U)

#define	HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)

#define	HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk

#define	HRTIM_SET1R_MSTCMP2_Pos (9U)

#define	HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)

#define	HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk

#define	HRTIM_SET1R_MSTCMP3_Pos (10U)

#define	HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)

#define	HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk

#define	HRTIM_SET1R_MSTCMP4_Pos (11U)

#define	HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)

#define	HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk

#define	HRTIM_SET1R_TIMEVNT1_Pos (12U)

#define	HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)

#define	HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk

#define	HRTIM_SET1R_TIMEVNT2_Pos (13U)

#define	HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)

#define	HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk

#define	HRTIM_SET1R_TIMEVNT3_Pos (14U)

#define	HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)

#define	HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk

#define	HRTIM_SET1R_TIMEVNT4_Pos (15U)

#define	HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)

#define	HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk

#define	HRTIM_SET1R_TIMEVNT5_Pos (16U)

#define	HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)

#define	HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk

#define	HRTIM_SET1R_TIMEVNT6_Pos (17U)

#define	HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)

#define	HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk

#define	HRTIM_SET1R_TIMEVNT7_Pos (18U)

#define	HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)

#define	HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk

#define	HRTIM_SET1R_TIMEVNT8_Pos (19U)

#define	HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)

#define	HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk

#define	HRTIM_SET1R_TIMEVNT9_Pos (20U)

#define	HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)

#define	HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk

#define	HRTIM_SET1R_EXTVNT1_Pos (21U)

#define	HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)

#define	HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk

#define	HRTIM_SET1R_EXTVNT2_Pos (22U)

#define	HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)

#define	HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk

#define	HRTIM_SET1R_EXTVNT3_Pos (23U)

#define	HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)

#define	HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk

#define	HRTIM_SET1R_EXTVNT4_Pos (24U)

#define	HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)

#define	HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk

#define	HRTIM_SET1R_EXTVNT5_Pos (25U)

#define	HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)

#define	HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk

#define	HRTIM_SET1R_EXTVNT6_Pos (26U)

#define	HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)

#define	HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk

#define	HRTIM_SET1R_EXTVNT7_Pos (27U)

#define	HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)

#define	HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk

#define	HRTIM_SET1R_EXTVNT8_Pos (28U)

#define	HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)

#define	HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk

#define	HRTIM_SET1R_EXTVNT9_Pos (29U)

#define	HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)

#define	HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk

#define	HRTIM_SET1R_EXTVNT10_Pos (30U)

#define	HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)

#define	HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk

#define	HRTIM_SET1R_UPDATE_Pos (31U)

#define	HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos)

#define	HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk

#define	HRTIM_RST1R_SRT_Pos (0U)

#define	HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos)

#define	HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk

#define	HRTIM_RST1R_RESYNC_Pos (1U)

#define	HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos)

#define	HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk

#define	HRTIM_RST1R_PER_Pos (2U)

#define	HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos)

#define	HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk

#define	HRTIM_RST1R_CMP1_Pos (3U)

#define	HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos)

#define	HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk

#define	HRTIM_RST1R_CMP2_Pos (4U)

#define	HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos)

#define	HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk

#define	HRTIM_RST1R_CMP3_Pos (5U)

#define	HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos)

#define	HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk

#define	HRTIM_RST1R_CMP4_Pos (6U)

#define	HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos)

#define	HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk

#define	HRTIM_RST1R_MSTPER_Pos (7U)

#define	HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos)

#define	HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk

#define	HRTIM_RST1R_MSTCMP1_Pos (8U)

#define	HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)

#define	HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk

#define	HRTIM_RST1R_MSTCMP2_Pos (9U)

#define	HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)

#define	HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk

#define	HRTIM_RST1R_MSTCMP3_Pos (10U)

#define	HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)

#define	HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk

#define	HRTIM_RST1R_MSTCMP4_Pos (11U)

#define	HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)

#define	HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk

#define	HRTIM_RST1R_TIMEVNT1_Pos (12U)

#define	HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)

#define	HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk

#define	HRTIM_RST1R_TIMEVNT2_Pos (13U)

#define	HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)

#define	HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk

#define	HRTIM_RST1R_TIMEVNT3_Pos (14U)

#define	HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)

#define	HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk

#define	HRTIM_RST1R_TIMEVNT4_Pos (15U)

#define	HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)

#define	HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk

#define	HRTIM_RST1R_TIMEVNT5_Pos (16U)

#define	HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)

#define	HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk

#define	HRTIM_RST1R_TIMEVNT6_Pos (17U)

#define	HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)

#define	HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk

#define	HRTIM_RST1R_TIMEVNT7_Pos (18U)

#define	HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)

#define	HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk

#define	HRTIM_RST1R_TIMEVNT8_Pos (19U)

#define	HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)

#define	HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk

#define	HRTIM_RST1R_TIMEVNT9_Pos (20U)

#define	HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)

#define	HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk

#define	HRTIM_RST1R_EXTVNT1_Pos (21U)

#define	HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)

#define	HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk

#define	HRTIM_RST1R_EXTVNT2_Pos (22U)

#define	HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)

#define	HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk

#define	HRTIM_RST1R_EXTVNT3_Pos (23U)

#define	HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)

#define	HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk

#define	HRTIM_RST1R_EXTVNT4_Pos (24U)

#define	HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)

#define	HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk

#define	HRTIM_RST1R_EXTVNT5_Pos (25U)

#define	HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)

#define	HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk

#define	HRTIM_RST1R_EXTVNT6_Pos (26U)

#define	HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)

#define	HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk

#define	HRTIM_RST1R_EXTVNT7_Pos (27U)

#define	HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)

#define	HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk

#define	HRTIM_RST1R_EXTVNT8_Pos (28U)

#define	HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)

#define	HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk

#define	HRTIM_RST1R_EXTVNT9_Pos (29U)

#define	HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)

#define	HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk

#define	HRTIM_RST1R_EXTVNT10_Pos (30U)

#define	HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)

#define	HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk

#define	HRTIM_RST1R_UPDATE_Pos (31U)

#define	HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos)

#define	HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk

#define	HRTIM_SET2R_SST_Pos (0U)

#define	HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos)

#define	HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk

#define	HRTIM_SET2R_RESYNC_Pos (1U)

#define	HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos)

#define	HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk

#define	HRTIM_SET2R_PER_Pos (2U)

#define	HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos)

#define	HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk

#define	HRTIM_SET2R_CMP1_Pos (3U)

#define	HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos)

#define	HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk

#define	HRTIM_SET2R_CMP2_Pos (4U)

#define	HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)

#define	HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk

#define	HRTIM_SET2R_CMP3_Pos (5U)

#define	HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos)

#define	HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk

#define	HRTIM_SET2R_CMP4_Pos (6U)

#define	HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos)

#define	HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk

#define	HRTIM_SET2R_MSTPER_Pos (7U)

#define	HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos)

#define	HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk

#define	HRTIM_SET2R_MSTCMP1_Pos (8U)

#define	HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)

#define	HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk

#define	HRTIM_SET2R_MSTCMP2_Pos (9U)

#define	HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)

#define	HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk

#define	HRTIM_SET2R_MSTCMP3_Pos (10U)

#define	HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)

#define	HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk

#define	HRTIM_SET2R_MSTCMP4_Pos (11U)

#define	HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)

#define	HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk

#define	HRTIM_SET2R_TIMEVNT1_Pos (12U)

#define	HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)

#define	HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk

#define	HRTIM_SET2R_TIMEVNT2_Pos (13U)

#define	HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)

#define	HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk

#define	HRTIM_SET2R_TIMEVNT3_Pos (14U)

#define	HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)

#define	HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk

#define	HRTIM_SET2R_TIMEVNT4_Pos (15U)

#define	HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)

#define	HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk

#define	HRTIM_SET2R_TIMEVNT5_Pos (16U)

#define	HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)

#define	HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk

#define	HRTIM_SET2R_TIMEVNT6_Pos (17U)

#define	HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)

#define	HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk

#define	HRTIM_SET2R_TIMEVNT7_Pos (18U)

#define	HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)

#define	HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk

#define	HRTIM_SET2R_TIMEVNT8_Pos (19U)

#define	HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)

#define	HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk

#define	HRTIM_SET2R_TIMEVNT9_Pos (20U)

#define	HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)

#define	HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk

#define	HRTIM_SET2R_EXTVNT1_Pos (21U)

#define	HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)

#define	HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk

#define	HRTIM_SET2R_EXTVNT2_Pos (22U)

#define	HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)

#define	HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk

#define	HRTIM_SET2R_EXTVNT3_Pos (23U)

#define	HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)

#define	HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk

#define	HRTIM_SET2R_EXTVNT4_Pos (24U)

#define	HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)

#define	HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk

#define	HRTIM_SET2R_EXTVNT5_Pos (25U)

#define	HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)

#define	HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk

#define	HRTIM_SET2R_EXTVNT6_Pos (26U)

#define	HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)

#define	HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk

#define	HRTIM_SET2R_EXTVNT7_Pos (27U)

#define	HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)

#define	HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk

#define	HRTIM_SET2R_EXTVNT8_Pos (28U)

#define	HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)

#define	HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk

#define	HRTIM_SET2R_EXTVNT9_Pos (29U)

#define	HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)

#define	HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk

#define	HRTIM_SET2R_EXTVNT10_Pos (30U)

#define	HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)

#define	HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk

#define	HRTIM_SET2R_UPDATE_Pos (31U)

#define	HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos)

#define	HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk

#define	HRTIM_RST2R_SRT_Pos (0U)

#define	HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos)

#define	HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk

#define	HRTIM_RST2R_RESYNC_Pos (1U)

#define	HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos)

#define	HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk

#define	HRTIM_RST2R_PER_Pos (2U)

#define	HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos)

#define	HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk

#define	HRTIM_RST2R_CMP1_Pos (3U)

#define	HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos)

#define	HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk

#define	HRTIM_RST2R_CMP2_Pos (4U)

#define	HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos)

#define	HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk

#define	HRTIM_RST2R_CMP3_Pos (5U)

#define	HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos)

#define	HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk

#define	HRTIM_RST2R_CMP4_Pos (6U)

#define	HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos)

#define	HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk

#define	HRTIM_RST2R_MSTPER_Pos (7U)

#define	HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos)

#define	HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk

#define	HRTIM_RST2R_MSTCMP1_Pos (8U)

#define	HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)

#define	HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk

#define	HRTIM_RST2R_MSTCMP2_Pos (9U)

#define	HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)

#define	HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk

#define	HRTIM_RST2R_MSTCMP3_Pos (10U)

#define	HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)

#define	HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk

#define	HRTIM_RST2R_MSTCMP4_Pos (11U)

#define	HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)

#define	HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk

#define	HRTIM_RST2R_TIMEVNT1_Pos (12U)

#define	HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)

#define	HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk

#define	HRTIM_RST2R_TIMEVNT2_Pos (13U)

#define	HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)

#define	HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk

#define	HRTIM_RST2R_TIMEVNT3_Pos (14U)

#define	HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)

#define	HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk

#define	HRTIM_RST2R_TIMEVNT4_Pos (15U)

#define	HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)

#define	HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk

#define	HRTIM_RST2R_TIMEVNT5_Pos (16U)

#define	HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)

#define	HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk

#define	HRTIM_RST2R_TIMEVNT6_Pos (17U)

#define	HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)

#define	HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk

#define	HRTIM_RST2R_TIMEVNT7_Pos (18U)

#define	HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)

#define	HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk

#define	HRTIM_RST2R_TIMEVNT8_Pos (19U)

#define	HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)

#define	HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk

#define	HRTIM_RST2R_TIMEVNT9_Pos (20U)

#define	HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)

#define	HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk

#define	HRTIM_RST2R_EXTVNT1_Pos (21U)

#define	HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)

#define	HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk

#define	HRTIM_RST2R_EXTVNT2_Pos (22U)

#define	HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)

#define	HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk

#define	HRTIM_RST2R_EXTVNT3_Pos (23U)

#define	HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)

#define	HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk

#define	HRTIM_RST2R_EXTVNT4_Pos (24U)

#define	HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)

#define	HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk

#define	HRTIM_RST2R_EXTVNT5_Pos (25U)

#define	HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)

#define	HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk

#define	HRTIM_RST2R_EXTVNT6_Pos (26U)

#define	HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)

#define	HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk

#define	HRTIM_RST2R_EXTVNT7_Pos (27U)

#define	HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)

#define	HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk

#define	HRTIM_RST2R_EXTVNT8_Pos (28U)

#define	HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)

#define	HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk

#define	HRTIM_RST2R_EXTVNT9_Pos (29U)

#define	HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)

#define	HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk

#define	HRTIM_RST2R_EXTVNT10_Pos (30U)

#define	HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)

#define	HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk

#define	HRTIM_RST2R_UPDATE_Pos (31U)

#define	HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos)

#define	HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk

#define	HRTIM_EEFR1_EE1LTCH_Pos (0U)

#define	HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)

#define	HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk

#define	HRTIM_EEFR1_EE1FLTR_Pos (1U)

#define	HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)

#define	HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk

#define	HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)

#define	HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)

#define	HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)

#define	HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)

#define	HRTIM_EEFR1_EE2LTCH_Pos (6U)

#define	HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)

#define	HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk

#define	HRTIM_EEFR1_EE2FLTR_Pos (7U)

#define	HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)

#define	HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk

#define	HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)

#define	HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)

#define	HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)

#define	HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)

#define	HRTIM_EEFR1_EE3LTCH_Pos (12U)

#define	HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)

#define	HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk

#define	HRTIM_EEFR1_EE3FLTR_Pos (13U)

#define	HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)

#define	HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk

#define	HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)

#define	HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)

#define	HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)

#define	HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)

#define	HRTIM_EEFR1_EE4LTCH_Pos (18U)

#define	HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)

#define	HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk

#define	HRTIM_EEFR1_EE4FLTR_Pos (19U)

#define	HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)

#define	HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk

#define	HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)

#define	HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)

#define	HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)

#define	HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)

#define	HRTIM_EEFR1_EE5LTCH_Pos (24U)

#define	HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)

#define	HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk

#define	HRTIM_EEFR1_EE5FLTR_Pos (25U)

#define	HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)

#define	HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk

#define	HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)

#define	HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)

#define	HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)

#define	HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)

#define	HRTIM_EEFR2_EE6LTCH_Pos (0U)

#define	HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)

#define	HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk

#define	HRTIM_EEFR2_EE6FLTR_Pos (1U)

#define	HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)

#define	HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk

#define	HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)

#define	HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)

#define	HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)

#define	HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)

#define	HRTIM_EEFR2_EE7LTCH_Pos (6U)

#define	HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)

#define	HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk

#define	HRTIM_EEFR2_EE7FLTR_Pos (7U)

#define	HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)

#define	HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk

#define	HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)

#define	HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)

#define	HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)

#define	HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)

#define	HRTIM_EEFR2_EE8LTCH_Pos (12U)

#define	HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)

#define	HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk

#define	HRTIM_EEFR2_EE8FLTR_Pos (13U)

#define	HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)

#define	HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk

#define	HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)

#define	HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)

#define	HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)

#define	HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)

#define	HRTIM_EEFR2_EE9LTCH_Pos (18U)

#define	HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)

#define	HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk

#define	HRTIM_EEFR2_EE9FLTR_Pos (19U)

#define	HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)

#define	HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk

#define	HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)

#define	HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)

#define	HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)

#define	HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)

#define	HRTIM_EEFR2_EE10LTCH_Pos (24U)

#define	HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)

#define	HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk

#define	HRTIM_EEFR2_EE10FLTR_Pos (25U)

#define	HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)

#define	HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk

#define	HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)

#define	HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)

#define	HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)

#define	HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)

#define	HRTIM_RSTR_UPDATE_Pos (1U)

#define	HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos)

#define	HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk

#define	HRTIM_RSTR_CMP2_Pos (2U)

#define	HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos)

#define	HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk

#define	HRTIM_RSTR_CMP4_Pos (3U)

#define	HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos)

#define	HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk

#define	HRTIM_RSTR_MSTPER_Pos (4U)

#define	HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos)

#define	HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk

#define	HRTIM_RSTR_MSTCMP1_Pos (5U)

#define	HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)

#define	HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk

#define	HRTIM_RSTR_MSTCMP2_Pos (6U)

#define	HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)

#define	HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk

#define	HRTIM_RSTR_MSTCMP3_Pos (7U)

#define	HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)

#define	HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk

#define	HRTIM_RSTR_MSTCMP4_Pos (8U)

#define	HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)

#define	HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk

#define	HRTIM_RSTR_EXTEVNT1_Pos (9U)

#define	HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)

#define	HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk

#define	HRTIM_RSTR_EXTEVNT2_Pos (10U)

#define	HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)

#define	HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk

#define	HRTIM_RSTR_EXTEVNT3_Pos (11U)

#define	HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)

#define	HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk

#define	HRTIM_RSTR_EXTEVNT4_Pos (12U)

#define	HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)

#define	HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk

#define	HRTIM_RSTR_EXTEVNT5_Pos (13U)

#define	HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)

#define	HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk

#define	HRTIM_RSTR_EXTEVNT6_Pos (14U)

#define	HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)

#define	HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk

#define	HRTIM_RSTR_EXTEVNT7_Pos (15U)

#define	HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)

#define	HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk

#define	HRTIM_RSTR_EXTEVNT8_Pos (16U)

#define	HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)

#define	HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk

#define	HRTIM_RSTR_EXTEVNT9_Pos (17U)

#define	HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)

#define	HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk

#define	HRTIM_RSTR_EXTEVNT10_Pos (18U)

#define	HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)

#define	HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk

#define	HRTIM_RSTR_TIMBCMP1_Pos (19U)

#define	HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)

#define	HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk

#define	HRTIM_RSTR_TIMBCMP2_Pos (20U)

#define	HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)

#define	HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk

#define	HRTIM_RSTR_TIMBCMP4_Pos (21U)

#define	HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)

#define	HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk

#define	HRTIM_RSTR_TIMCCMP1_Pos (22U)

#define	HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)

#define	HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk

#define	HRTIM_RSTR_TIMCCMP2_Pos (23U)

#define	HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)

#define	HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk

#define	HRTIM_RSTR_TIMCCMP4_Pos (24U)

#define	HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)

#define	HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk

#define	HRTIM_RSTR_TIMDCMP1_Pos (25U)

#define	HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)

#define	HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk

#define	HRTIM_RSTR_TIMDCMP2_Pos (26U)

#define	HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)

#define	HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk

#define	HRTIM_RSTR_TIMDCMP4_Pos (27U)

#define	HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)

#define	HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk

#define	HRTIM_RSTR_TIMECMP1_Pos (28U)

#define	HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)

#define	HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk

#define	HRTIM_RSTR_TIMECMP2_Pos (29U)

#define	HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)

#define	HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk

#define	HRTIM_RSTR_TIMECMP4_Pos (30U)

#define	HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)

#define	HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk

#define	HRTIM_CHPR_CARFRQ_Pos (0U)

#define	HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos)

#define	HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk

#define	HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos)

#define	HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos)

#define	HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos)

#define	HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos)

#define	HRTIM_CHPR_CARDTY_Pos (4U)

#define	HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos)

#define	HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk

#define	HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos)

#define	HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos)

#define	HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos)

#define	HRTIM_CHPR_STRPW_Pos (7U)

#define	HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos)

#define	HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk

#define	HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos)

#define	HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos)

#define	HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos)

#define	HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos)

#define	HRTIM_CPT1CR_SWCPT_Pos (0U)

#define	HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)

#define	HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk

#define	HRTIM_CPT1CR_UPDCPT_Pos (1U)

#define	HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)

#define	HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk

#define	HRTIM_CPT1CR_EXEV1CPT_Pos (2U)

#define	HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)

#define	HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk

#define	HRTIM_CPT1CR_EXEV2CPT_Pos (3U)

#define	HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)

#define	HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk

#define	HRTIM_CPT1CR_EXEV3CPT_Pos (4U)

#define	HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)

#define	HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk

#define	HRTIM_CPT1CR_EXEV4CPT_Pos (5U)

#define	HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)

#define	HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk

#define	HRTIM_CPT1CR_EXEV5CPT_Pos (6U)

#define	HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)

#define	HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk

#define	HRTIM_CPT1CR_EXEV6CPT_Pos (7U)

#define	HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)

#define	HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk

#define	HRTIM_CPT1CR_EXEV7CPT_Pos (8U)

#define	HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)

#define	HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk

#define	HRTIM_CPT1CR_EXEV8CPT_Pos (9U)

#define	HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)

#define	HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk

#define	HRTIM_CPT1CR_EXEV9CPT_Pos (10U)

#define	HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)

#define	HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk

#define	HRTIM_CPT1CR_EXEV10CPT_Pos (11U)

#define	HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)

#define	HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk

#define	HRTIM_CPT1CR_TA1SET_Pos (12U)

#define	HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)

#define	HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk

#define	HRTIM_CPT1CR_TA1RST_Pos (13U)

#define	HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)

#define	HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk

#define	HRTIM_CPT1CR_TIMACMP1_Pos (14U)

#define	HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)

#define	HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk

#define	HRTIM_CPT1CR_TIMACMP2_Pos (15U)

#define	HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)

#define	HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk

#define	HRTIM_CPT1CR_TB1SET_Pos (16U)

#define	HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)

#define	HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk

#define	HRTIM_CPT1CR_TB1RST_Pos (17U)

#define	HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)

#define	HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk

#define	HRTIM_CPT1CR_TIMBCMP1_Pos (18U)

#define	HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)

#define	HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk

#define	HRTIM_CPT1CR_TIMBCMP2_Pos (19U)

#define	HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)

#define	HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk

#define	HRTIM_CPT1CR_TC1SET_Pos (20U)

#define	HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)

#define	HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk

#define	HRTIM_CPT1CR_TC1RST_Pos (21U)

#define	HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)

#define	HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk

#define	HRTIM_CPT1CR_TIMCCMP1_Pos (22U)

#define	HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)

#define	HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk

#define	HRTIM_CPT1CR_TIMCCMP2_Pos (23U)

#define	HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)

#define	HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk

#define	HRTIM_CPT1CR_TD1SET_Pos (24U)

#define	HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)

#define	HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk

#define	HRTIM_CPT1CR_TD1RST_Pos (25U)

#define	HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)

#define	HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk

#define	HRTIM_CPT1CR_TIMDCMP1_Pos (26U)

#define	HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)

#define	HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk

#define	HRTIM_CPT1CR_TIMDCMP2_Pos (27U)

#define	HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)

#define	HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk

#define	HRTIM_CPT1CR_TE1SET_Pos (28U)

#define	HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)

#define	HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk

#define	HRTIM_CPT1CR_TE1RST_Pos (29U)

#define	HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)

#define	HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk

#define	HRTIM_CPT1CR_TIMECMP1_Pos (30U)

#define	HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)

#define	HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk

#define	HRTIM_CPT1CR_TIMECMP2_Pos (31U)

#define	HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)

#define	HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk

#define	HRTIM_CPT2CR_SWCPT_Pos (0U)

#define	HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)

#define	HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk

#define	HRTIM_CPT2CR_UPDCPT_Pos (1U)

#define	HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)

#define	HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk

#define	HRTIM_CPT2CR_EXEV1CPT_Pos (2U)

#define	HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)

#define	HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk

#define	HRTIM_CPT2CR_EXEV2CPT_Pos (3U)

#define	HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)

#define	HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk

#define	HRTIM_CPT2CR_EXEV3CPT_Pos (4U)

#define	HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)

#define	HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk

#define	HRTIM_CPT2CR_EXEV4CPT_Pos (5U)

#define	HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)

#define	HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk

#define	HRTIM_CPT2CR_EXEV5CPT_Pos (6U)

#define	HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)

#define	HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk

#define	HRTIM_CPT2CR_EXEV6CPT_Pos (7U)

#define	HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)

#define	HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk

#define	HRTIM_CPT2CR_EXEV7CPT_Pos (8U)

#define	HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)

#define	HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk

#define	HRTIM_CPT2CR_EXEV8CPT_Pos (9U)

#define	HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)

#define	HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk

#define	HRTIM_CPT2CR_EXEV9CPT_Pos (10U)

#define	HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)

#define	HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk

#define	HRTIM_CPT2CR_EXEV10CPT_Pos (11U)

#define	HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)

#define	HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk

#define	HRTIM_CPT2CR_TA1SET_Pos (12U)

#define	HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)

#define	HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk

#define	HRTIM_CPT2CR_TA1RST_Pos (13U)

#define	HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)

#define	HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk

#define	HRTIM_CPT2CR_TIMACMP1_Pos (14U)

#define	HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)

#define	HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk

#define	HRTIM_CPT2CR_TIMACMP2_Pos (15U)

#define	HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)

#define	HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk

#define	HRTIM_CPT2CR_TB1SET_Pos (16U)

#define	HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)

#define	HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk

#define	HRTIM_CPT2CR_TB1RST_Pos (17U)

#define	HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)

#define	HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk

#define	HRTIM_CPT2CR_TIMBCMP1_Pos (18U)

#define	HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)

#define	HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk

#define	HRTIM_CPT2CR_TIMBCMP2_Pos (19U)

#define	HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)

#define	HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk

#define	HRTIM_CPT2CR_TC1SET_Pos (20U)

#define	HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)

#define	HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk

#define	HRTIM_CPT2CR_TC1RST_Pos (21U)

#define	HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)

#define	HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk

#define	HRTIM_CPT2CR_TIMCCMP1_Pos (22U)

#define	HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)

#define	HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk

#define	HRTIM_CPT2CR_TIMCCMP2_Pos (23U)

#define	HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)

#define	HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk

#define	HRTIM_CPT2CR_TD1SET_Pos (24U)

#define	HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)

#define	HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk

#define	HRTIM_CPT2CR_TD1RST_Pos (25U)

#define	HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)

#define	HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk

#define	HRTIM_CPT2CR_TIMDCMP1_Pos (26U)

#define	HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)

#define	HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk

#define	HRTIM_CPT2CR_TIMDCMP2_Pos (27U)

#define	HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)

#define	HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk

#define	HRTIM_CPT2CR_TE1SET_Pos (28U)

#define	HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)

#define	HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk

#define	HRTIM_CPT2CR_TE1RST_Pos (29U)

#define	HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)

#define	HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk

#define	HRTIM_CPT2CR_TIMECMP1_Pos (30U)

#define	HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)

#define	HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk

#define	HRTIM_CPT2CR_TIMECMP2_Pos (31U)

#define	HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)

#define	HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk

#define	HRTIM_OUTR_POL1_Pos (1U)

#define	HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos)

#define	HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk

#define	HRTIM_OUTR_IDLM1_Pos (2U)

#define	HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos)

#define	HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk

#define	HRTIM_OUTR_IDLES1_Pos (3U)

#define	HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos)

#define	HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk

#define	HRTIM_OUTR_FAULT1_Pos (4U)

#define	HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos)

#define	HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk

#define	HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos)

#define	HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos)

#define	HRTIM_OUTR_CHP1_Pos (6U)

#define	HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos)

#define	HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk

#define	HRTIM_OUTR_DIDL1_Pos (7U)

#define	HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos)

#define	HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk

#define	HRTIM_OUTR_DTEN_Pos (8U)

#define	HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos)

#define	HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk

#define	HRTIM_OUTR_DLYPRTEN_Pos (9U)

#define	HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)

#define	HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk

#define	HRTIM_OUTR_DLYPRT_Pos (10U)

#define	HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos)

#define	HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk

#define	HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos)

#define	HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos)

#define	HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos)

#define	HRTIM_OUTR_POL2_Pos (17U)

#define	HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos)

#define	HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk

#define	HRTIM_OUTR_IDLM2_Pos (18U)

#define	HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos)

#define	HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk

#define	HRTIM_OUTR_IDLES2_Pos (19U)

#define	HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos)

#define	HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk

#define	HRTIM_OUTR_FAULT2_Pos (20U)

#define	HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos)

#define	HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk

#define	HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos)

#define	HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos)

#define	HRTIM_OUTR_CHP2_Pos (22U)

#define	HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos)

#define	HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk

#define	HRTIM_OUTR_DIDL2_Pos (23U)

#define	HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos)

#define	HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk

#define	HRTIM_FLTR_FLT1EN_Pos (0U)

#define	HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos)

#define	HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk

#define	HRTIM_FLTR_FLT2EN_Pos (1U)

#define	HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos)

#define	HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk

#define	HRTIM_FLTR_FLT3EN_Pos (2U)

#define	HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos)

#define	HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk

#define	HRTIM_FLTR_FLT4EN_Pos (3U)

#define	HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos)

#define	HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk

#define	HRTIM_FLTR_FLT5EN_Pos (4U)

#define	HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos)

#define	HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk

#define	HRTIM_FLTR_FLTLCK_Pos (31U)

#define	HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos)

#define	HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk

#define	HRTIM_CR1_MUDIS_Pos (0U)

#define	HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos)

#define	HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk

#define	HRTIM_CR1_TAUDIS_Pos (1U)

#define	HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos)

#define	HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk

#define	HRTIM_CR1_TBUDIS_Pos (2U)

#define	HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos)

#define	HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk

#define	HRTIM_CR1_TCUDIS_Pos (3U)

#define	HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos)

#define	HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk

#define	HRTIM_CR1_TDUDIS_Pos (4U)

#define	HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos)

#define	HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk

#define	HRTIM_CR1_TEUDIS_Pos (5U)

#define	HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos)

#define	HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk

#define	HRTIM_CR1_ADC1USRC_Pos (16U)

#define	HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos)

#define	HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk

#define	HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos)

#define	HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos)

#define	HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos)

#define	HRTIM_CR1_ADC2USRC_Pos (19U)

#define	HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos)

#define	HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk

#define	HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos)

#define	HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos)

#define	HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos)

#define	HRTIM_CR1_ADC3USRC_Pos (22U)

#define	HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos)

#define	HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk

#define	HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos)

#define	HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos)

#define	HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos)

#define	HRTIM_CR1_ADC4USRC_Pos (25U)

#define	HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos)

#define	HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk

#define	HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos)

#define	HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos)

#define	HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos)

#define	HRTIM_CR2_MSWU_Pos (0U)

#define	HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos)

#define	HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk

#define	HRTIM_CR2_TASWU_Pos (1U)

#define	HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos)

#define	HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk

#define	HRTIM_CR2_TBSWU_Pos (2U)

#define	HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos)

#define	HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk

#define	HRTIM_CR2_TCSWU_Pos (3U)

#define	HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos)

#define	HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk

#define	HRTIM_CR2_TDSWU_Pos (4U)

#define	HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos)

#define	HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk

#define	HRTIM_CR2_TESWU_Pos (5U)

#define	HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos)

#define	HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk

#define	HRTIM_CR2_MRST_Pos (8U)

#define	HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos)

#define	HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk

#define	HRTIM_CR2_TARST_Pos (9U)

#define	HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos)

#define	HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk

#define	HRTIM_CR2_TBRST_Pos (10U)

#define	HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos)

#define	HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk

#define	HRTIM_CR2_TCRST_Pos (11U)

#define	HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos)

#define	HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk

#define	HRTIM_CR2_TDRST_Pos (12U)

#define	HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos)

#define	HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk

#define	HRTIM_CR2_TERST_Pos (13U)

#define	HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos)

#define	HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk

#define	HRTIM_ISR_FLT1_Pos (0U)

#define	HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos)

#define	HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk

#define	HRTIM_ISR_FLT2_Pos (1U)

#define	HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos)

#define	HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk

#define	HRTIM_ISR_FLT3_Pos (2U)

#define	HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos)

#define	HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk

#define	HRTIM_ISR_FLT4_Pos (3U)

#define	HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos)

#define	HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk

#define	HRTIM_ISR_FLT5_Pos (4U)

#define	HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos)

#define	HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk

#define	HRTIM_ISR_SYSFLT_Pos (5U)

#define	HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos)

#define	HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk

#define	HRTIM_ISR_DLLRDY_Pos (16U)

#define	HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos)

#define	HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk

#define	HRTIM_ISR_BMPER_Pos (17U)

#define	HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos)

#define	HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk

#define	HRTIM_ICR_FLT1C_Pos (0U)

#define	HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos)

#define	HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk

#define	HRTIM_ICR_FLT2C_Pos (1U)

#define	HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos)

#define	HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk

#define	HRTIM_ICR_FLT3C_Pos (2U)

#define	HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos)

#define	HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk

#define	HRTIM_ICR_FLT4C_Pos (3U)

#define	HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos)

#define	HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk

#define	HRTIM_ICR_FLT5C_Pos (4U)

#define	HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos)

#define	HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk

#define	HRTIM_ICR_SYSFLTC_Pos (5U)

#define	HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos)

#define	HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk

#define	HRTIM_ICR_DLLRDYC_Pos (16U)

#define	HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos)

#define	HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk

#define	HRTIM_ICR_BMPERC_Pos (17U)

#define	HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos)

#define	HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk

#define	HRTIM_IER_FLT1_Pos (0U)

#define	HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos)

#define	HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk

#define	HRTIM_IER_FLT2_Pos (1U)

#define	HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos)

#define	HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk

#define	HRTIM_IER_FLT3_Pos (2U)

#define	HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos)

#define	HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk

#define	HRTIM_IER_FLT4_Pos (3U)

#define	HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos)

#define	HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk

#define	HRTIM_IER_FLT5_Pos (4U)

#define	HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos)

#define	HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk

#define	HRTIM_IER_SYSFLT_Pos (5U)

#define	HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos)

#define	HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk

#define	HRTIM_IER_DLLRDY_Pos (16U)

#define	HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos)

#define	HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk

#define	HRTIM_IER_BMPER_Pos (17U)

#define	HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos)

#define	HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk

#define	HRTIM_OENR_TA1OEN_Pos (0U)

#define	HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)

#define	HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk

#define	HRTIM_OENR_TA2OEN_Pos (1U)

#define	HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos)

#define	HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk

#define	HRTIM_OENR_TB1OEN_Pos (2U)

#define	HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos)

#define	HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk

#define	HRTIM_OENR_TB2OEN_Pos (3U)

#define	HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos)

#define	HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk

#define	HRTIM_OENR_TC1OEN_Pos (4U)

#define	HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos)

#define	HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk

#define	HRTIM_OENR_TC2OEN_Pos (5U)

#define	HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos)

#define	HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk

#define	HRTIM_OENR_TD1OEN_Pos (6U)

#define	HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos)

#define	HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk

#define	HRTIM_OENR_TD2OEN_Pos (7U)

#define	HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos)

#define	HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk

#define	HRTIM_OENR_TE1OEN_Pos (8U)

#define	HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos)

#define	HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk

#define	HRTIM_OENR_TE2OEN_Pos (9U)

#define	HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos)

#define	HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk

#define	HRTIM_ODISR_TA1ODIS_Pos (0U)

#define	HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)

#define	HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk

#define	HRTIM_ODISR_TA2ODIS_Pos (1U)

#define	HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)

#define	HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk

#define	HRTIM_ODISR_TB1ODIS_Pos (2U)

#define	HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)

#define	HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk

#define	HRTIM_ODISR_TB2ODIS_Pos (3U)

#define	HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)

#define	HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk

#define	HRTIM_ODISR_TC1ODIS_Pos (4U)

#define	HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)

#define	HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk

#define	HRTIM_ODISR_TC2ODIS_Pos (5U)

#define	HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)

#define	HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk

#define	HRTIM_ODISR_TD1ODIS_Pos (6U)

#define	HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)

#define	HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk

#define	HRTIM_ODISR_TD2ODIS_Pos (7U)

#define	HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)

#define	HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk

#define	HRTIM_ODISR_TE1ODIS_Pos (8U)

#define	HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)

#define	HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk

#define	HRTIM_ODISR_TE2ODIS_Pos (9U)

#define	HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)

#define	HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk

#define	HRTIM_ODSR_TA1ODS_Pos (0U)

#define	HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos)

#define	HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk

#define	HRTIM_ODSR_TA2ODS_Pos (1U)

#define	HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos)

#define	HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk

#define	HRTIM_ODSR_TB1ODS_Pos (2U)

#define	HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos)

#define	HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk

#define	HRTIM_ODSR_TB2ODS_Pos (3U)

#define	HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos)

#define	HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk

#define	HRTIM_ODSR_TC1ODS_Pos (4U)

#define	HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos)

#define	HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk

#define	HRTIM_ODSR_TC2ODS_Pos (5U)

#define	HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos)

#define	HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk

#define	HRTIM_ODSR_TD1ODS_Pos (6U)

#define	HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos)

#define	HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk

#define	HRTIM_ODSR_TD2ODS_Pos (7U)

#define	HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos)

#define	HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk

#define	HRTIM_ODSR_TE1ODS_Pos (8U)

#define	HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos)

#define	HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk

#define	HRTIM_ODSR_TE2ODS_Pos (9U)

#define	HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos)

#define	HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk

#define	HRTIM_BMCR_BME_Pos (0U)

#define	HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos)

#define	HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk

#define	HRTIM_BMCR_BMOM_Pos (1U)

#define	HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos)

#define	HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk

#define	HRTIM_BMCR_BMCLK_Pos (2U)

#define	HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos)

#define	HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk

#define	HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos)

#define	HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos)

#define	HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos)

#define	HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos)

#define	HRTIM_BMCR_BMPRSC_Pos (6U)

#define	HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos)

#define	HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk

#define	HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos)

#define	HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos)

#define	HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos)

#define	HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos)

#define	HRTIM_BMCR_BMPREN_Pos (10U)

#define	HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos)

#define	HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk

#define	HRTIM_BMCR_MTBM_Pos (16U)

#define	HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos)

#define	HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk

#define	HRTIM_BMCR_TABM_Pos (17U)

#define	HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos)

#define	HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk

#define	HRTIM_BMCR_TBBM_Pos (18U)

#define	HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos)

#define	HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk

#define	HRTIM_BMCR_TCBM_Pos (19U)

#define	HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)

#define	HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk

#define	HRTIM_BMCR_TDBM_Pos (20U)

#define	HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos)

#define	HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk

#define	HRTIM_BMCR_TEBM_Pos (21U)

#define	HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos)

#define	HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk

#define	HRTIM_BMCR_BMSTAT_Pos (31U)

#define	HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos)

#define	HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk

#define	HRTIM_BMTRGR_SW_Pos (0U)

#define	HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos)

#define	HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk

#define	HRTIM_BMTRGR_MSTRST_Pos (1U)

#define	HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)

#define	HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk

#define	HRTIM_BMTRGR_MSTREP_Pos (2U)

#define	HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)

#define	HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk

#define	HRTIM_BMTRGR_MSTCMP1_Pos (3U)

#define	HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)

#define	HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk

#define	HRTIM_BMTRGR_MSTCMP2_Pos (4U)

#define	HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)

#define	HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk

#define	HRTIM_BMTRGR_MSTCMP3_Pos (5U)

#define	HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)

#define	HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk

#define	HRTIM_BMTRGR_MSTCMP4_Pos (6U)

#define	HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)

#define	HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk

#define	HRTIM_BMTRGR_TARST_Pos (7U)

#define	HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos)

#define	HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk

#define	HRTIM_BMTRGR_TAREP_Pos (8U)

#define	HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos)

#define	HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk

#define	HRTIM_BMTRGR_TACMP1_Pos (9U)

#define	HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)

#define	HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk

#define	HRTIM_BMTRGR_TACMP2_Pos (10U)

#define	HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)

#define	HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk

#define	HRTIM_BMTRGR_TBRST_Pos (11U)

#define	HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos)

#define	HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk

#define	HRTIM_BMTRGR_TBREP_Pos (12U)

#define	HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos)

#define	HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk

#define	HRTIM_BMTRGR_TBCMP1_Pos (13U)

#define	HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)

#define	HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk

#define	HRTIM_BMTRGR_TBCMP2_Pos (14U)

#define	HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)

#define	HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk

#define	HRTIM_BMTRGR_TCRST_Pos (15U)

#define	HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos)

#define	HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk

#define	HRTIM_BMTRGR_TCREP_Pos (16U)

#define	HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos)

#define	HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk

#define	HRTIM_BMTRGR_TCCMP1_Pos (17U)

#define	HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)

#define	HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk

#define	HRTIM_BMTRGR_TCCMP2_Pos (18U)

#define	HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)

#define	HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk

#define	HRTIM_BMTRGR_TDRST_Pos (19U)

#define	HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos)

#define	HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk

#define	HRTIM_BMTRGR_TDREP_Pos (20U)

#define	HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos)

#define	HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk

#define	HRTIM_BMTRGR_TDCMP1_Pos (21U)

#define	HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)

#define	HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk

#define	HRTIM_BMTRGR_TDCMP2_Pos (22U)

#define	HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)

#define	HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk

#define	HRTIM_BMTRGR_TERST_Pos (23U)

#define	HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos)

#define	HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk

#define	HRTIM_BMTRGR_TEREP_Pos (24U)

#define	HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos)

#define	HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk

#define	HRTIM_BMTRGR_TECMP1_Pos (25U)

#define	HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)

#define	HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk

#define	HRTIM_BMTRGR_TECMP2_Pos (26U)

#define	HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)

#define	HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk

#define	HRTIM_BMTRGR_TAEEV7_Pos (27U)

#define	HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)

#define	HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk

#define	HRTIM_BMTRGR_TDEEV8_Pos (28U)

#define	HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)

#define	HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk

#define	HRTIM_BMTRGR_EEV7_Pos (29U)

#define	HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos)

#define	HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk

#define	HRTIM_BMTRGR_EEV8_Pos (30U)

#define	HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos)

#define	HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk

#define	HRTIM_BMTRGR_OCHPEV_Pos (31U)

#define	HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)

#define	HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk

#define	HRTIM_BMCMPR_BMCMPR_Pos (0U)

#define	HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)

#define	HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk

#define	HRTIM_BMPER_BMPER_Pos (0U)

#define	HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)

#define	HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk

#define	HRTIM_EECR1_EE1SRC_Pos (0U)

#define	HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos)

#define	HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk

#define	HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos)

#define	HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos)

#define	HRTIM_EECR1_EE1POL_Pos (2U)

#define	HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos)

#define	HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk

#define	HRTIM_EECR1_EE1SNS_Pos (3U)

#define	HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos)

#define	HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk

#define	HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos)

#define	HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos)

#define	HRTIM_EECR1_EE1FAST_Pos (5U)

#define	HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos)

#define	HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk

#define	HRTIM_EECR1_EE2SRC_Pos (6U)

#define	HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos)

#define	HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk

#define	HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos)

#define	HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos)

#define	HRTIM_EECR1_EE2POL_Pos (8U)

#define	HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos)

#define	HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk

#define	HRTIM_EECR1_EE2SNS_Pos (9U)

#define	HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos)

#define	HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk

#define	HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos)

#define	HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos)

#define	HRTIM_EECR1_EE2FAST_Pos (11U)

#define	HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos)

#define	HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk

#define	HRTIM_EECR1_EE3SRC_Pos (12U)

#define	HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos)

#define	HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk

#define	HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos)

#define	HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos)

#define	HRTIM_EECR1_EE3POL_Pos (14U)

#define	HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos)

#define	HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk

#define	HRTIM_EECR1_EE3SNS_Pos (15U)

#define	HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos)

#define	HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk

#define	HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos)

#define	HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos)

#define	HRTIM_EECR1_EE3FAST_Pos (17U)

#define	HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos)

#define	HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk

#define	HRTIM_EECR1_EE4SRC_Pos (18U)

#define	HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos)

#define	HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk

#define	HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos)

#define	HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos)

#define	HRTIM_EECR1_EE4POL_Pos (20U)

#define	HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos)

#define	HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk

#define	HRTIM_EECR1_EE4SNS_Pos (21U)

#define	HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos)

#define	HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk

#define	HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos)

#define	HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos)

#define	HRTIM_EECR1_EE4FAST_Pos (23U)

#define	HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos)

#define	HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk

#define	HRTIM_EECR1_EE5SRC_Pos (24U)

#define	HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos)

#define	HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk

#define	HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos)

#define	HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos)

#define	HRTIM_EECR1_EE5POL_Pos (26U)

#define	HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos)

#define	HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk

#define	HRTIM_EECR1_EE5SNS_Pos (27U)

#define	HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos)

#define	HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk

#define	HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos)

#define	HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos)

#define	HRTIM_EECR1_EE5FAST_Pos (29U)

#define	HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos)

#define	HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk

#define	HRTIM_EECR2_EE6SRC_Pos (0U)

#define	HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos)

#define	HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk

#define	HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos)

#define	HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos)

#define	HRTIM_EECR2_EE6POL_Pos (2U)

#define	HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos)

#define	HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk

#define	HRTIM_EECR2_EE6SNS_Pos (3U)

#define	HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos)

#define	HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk

#define	HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos)

#define	HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos)

#define	HRTIM_EECR2_EE7SRC_Pos (6U)

#define	HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos)

#define	HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk

#define	HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos)

#define	HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos)

#define	HRTIM_EECR2_EE7POL_Pos (8U)

#define	HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos)

#define	HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk

#define	HRTIM_EECR2_EE7SNS_Pos (9U)

#define	HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos)

#define	HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk

#define	HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos)

#define	HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos)

#define	HRTIM_EECR2_EE8SRC_Pos (12U)

#define	HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos)

#define	HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk

#define	HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos)

#define	HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos)

#define	HRTIM_EECR2_EE8POL_Pos (14U)

#define	HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos)

#define	HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk

#define	HRTIM_EECR2_EE8SNS_Pos (15U)

#define	HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos)

#define	HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk

#define	HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos)

#define	HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos)

#define	HRTIM_EECR2_EE9SRC_Pos (18U)

#define	HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos)

#define	HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk

#define	HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos)

#define	HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos)

#define	HRTIM_EECR2_EE9POL_Pos (20U)

#define	HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos)

#define	HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk

#define	HRTIM_EECR2_EE9SNS_Pos (21U)

#define	HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos)

#define	HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk

#define	HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos)

#define	HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos)

#define	HRTIM_EECR2_EE10SRC_Pos (24U)

#define	HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos)

#define	HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk

#define	HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos)

#define	HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos)

#define	HRTIM_EECR2_EE10POL_Pos (26U)

#define	HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos)

#define	HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk

#define	HRTIM_EECR2_EE10SNS_Pos (27U)

#define	HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos)

#define	HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk

#define	HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos)

#define	HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos)

#define	HRTIM_EECR3_EE6F_Pos (0U)

#define	HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos)

#define	HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk

#define	HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos)

#define	HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos)

#define	HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos)

#define	HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos)

#define	HRTIM_EECR3_EE7F_Pos (6U)

#define	HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos)

#define	HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk

#define	HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos)

#define	HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos)

#define	HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos)

#define	HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos)

#define	HRTIM_EECR3_EE8F_Pos (12U)

#define	HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos)

#define	HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk

#define	HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos)

#define	HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos)

#define	HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos)

#define	HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos)

#define	HRTIM_EECR3_EE9F_Pos (18U)

#define	HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos)

#define	HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk

#define	HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos)

#define	HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos)

#define	HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos)

#define	HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos)

#define	HRTIM_EECR3_EE10F_Pos (24U)

#define	HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos)

#define	HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk

#define	HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos)

#define	HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos)

#define	HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos)

#define	HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos)

#define	HRTIM_EECR3_EEVSD_Pos (30U)

#define	HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos)

#define	HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk

#define	HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos)

#define	HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos)

#define	HRTIM_ADC1R_AD1MC1_Pos (0U)

#define	HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)

#define	HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk

#define	HRTIM_ADC1R_AD1MC2_Pos (1U)

#define	HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)

#define	HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk

#define	HRTIM_ADC1R_AD1MC3_Pos (2U)

#define	HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)

#define	HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk

#define	HRTIM_ADC1R_AD1MC4_Pos (3U)

#define	HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)

#define	HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk

#define	HRTIM_ADC1R_AD1MPER_Pos (4U)

#define	HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)

#define	HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk

#define	HRTIM_ADC1R_AD1EEV1_Pos (5U)

#define	HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)

#define	HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk

#define	HRTIM_ADC1R_AD1EEV2_Pos (6U)

#define	HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)

#define	HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk

#define	HRTIM_ADC1R_AD1EEV3_Pos (7U)

#define	HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)

#define	HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk

#define	HRTIM_ADC1R_AD1EEV4_Pos (8U)

#define	HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)

#define	HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk

#define	HRTIM_ADC1R_AD1EEV5_Pos (9U)

#define	HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)

#define	HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk

#define	HRTIM_ADC1R_AD1TAC2_Pos (10U)

#define	HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)

#define	HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk

#define	HRTIM_ADC1R_AD1TAC3_Pos (11U)

#define	HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)

#define	HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk

#define	HRTIM_ADC1R_AD1TAC4_Pos (12U)

#define	HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)

#define	HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk

#define	HRTIM_ADC1R_AD1TAPER_Pos (13U)

#define	HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)

#define	HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk

#define	HRTIM_ADC1R_AD1TARST_Pos (14U)

#define	HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)

#define	HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk

#define	HRTIM_ADC1R_AD1TBC2_Pos (15U)

#define	HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)

#define	HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk

#define	HRTIM_ADC1R_AD1TBC3_Pos (16U)

#define	HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)

#define	HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk

#define	HRTIM_ADC1R_AD1TBC4_Pos (17U)

#define	HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)

#define	HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk

#define	HRTIM_ADC1R_AD1TBPER_Pos (18U)

#define	HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)

#define	HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk

#define	HRTIM_ADC1R_AD1TBRST_Pos (19U)

#define	HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)

#define	HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk

#define	HRTIM_ADC1R_AD1TCC2_Pos (20U)

#define	HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)

#define	HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk

#define	HRTIM_ADC1R_AD1TCC3_Pos (21U)

#define	HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)

#define	HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk

#define	HRTIM_ADC1R_AD1TCC4_Pos (22U)

#define	HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)

#define	HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk

#define	HRTIM_ADC1R_AD1TCPER_Pos (23U)

#define	HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)

#define	HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk

#define	HRTIM_ADC1R_AD1TDC2_Pos (24U)

#define	HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)

#define	HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk

#define	HRTIM_ADC1R_AD1TDC3_Pos (25U)

#define	HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)

#define	HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk

#define	HRTIM_ADC1R_AD1TDC4_Pos (26U)

#define	HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)

#define	HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk

#define	HRTIM_ADC1R_AD1TDPER_Pos (27U)

#define	HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)

#define	HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk

#define	HRTIM_ADC1R_AD1TEC2_Pos (28U)

#define	HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)

#define	HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk

#define	HRTIM_ADC1R_AD1TEC3_Pos (29U)

#define	HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)

#define	HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk

#define	HRTIM_ADC1R_AD1TEC4_Pos (30U)

#define	HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)

#define	HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk

#define	HRTIM_ADC1R_AD1TEPER_Pos (31U)

#define	HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)

#define	HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk

#define	HRTIM_ADC2R_AD2MC1_Pos (0U)

#define	HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)

#define	HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk

#define	HRTIM_ADC2R_AD2MC2_Pos (1U)

#define	HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)

#define	HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk

#define	HRTIM_ADC2R_AD2MC3_Pos (2U)

#define	HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)

#define	HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk

#define	HRTIM_ADC2R_AD2MC4_Pos (3U)

#define	HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)

#define	HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk

#define	HRTIM_ADC2R_AD2MPER_Pos (4U)

#define	HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)

#define	HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk

#define	HRTIM_ADC2R_AD2EEV6_Pos (5U)

#define	HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)

#define	HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk

#define	HRTIM_ADC2R_AD2EEV7_Pos (6U)

#define	HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)

#define	HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk

#define	HRTIM_ADC2R_AD2EEV8_Pos (7U)

#define	HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)

#define	HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk

#define	HRTIM_ADC2R_AD2EEV9_Pos (8U)

#define	HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)

#define	HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk

#define	HRTIM_ADC2R_AD2EEV10_Pos (9U)

#define	HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)

#define	HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk

#define	HRTIM_ADC2R_AD2TAC2_Pos (10U)

#define	HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)

#define	HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk

#define	HRTIM_ADC2R_AD2TAC3_Pos (11U)

#define	HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)

#define	HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk

#define	HRTIM_ADC2R_AD2TAC4_Pos (12U)

#define	HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)

#define	HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk

#define	HRTIM_ADC2R_AD2TAPER_Pos (13U)

#define	HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)

#define	HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk

#define	HRTIM_ADC2R_AD2TBC2_Pos (14U)

#define	HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)

#define	HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk

#define	HRTIM_ADC2R_AD2TBC3_Pos (15U)

#define	HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)

#define	HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk

#define	HRTIM_ADC2R_AD2TBC4_Pos (16U)

#define	HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)

#define	HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk

#define	HRTIM_ADC2R_AD2TBPER_Pos (17U)

#define	HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)

#define	HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk

#define	HRTIM_ADC2R_AD2TCC2_Pos (18U)

#define	HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)

#define	HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk

#define	HRTIM_ADC2R_AD2TCC3_Pos (19U)

#define	HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)

#define	HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk

#define	HRTIM_ADC2R_AD2TCC4_Pos (20U)

#define	HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)

#define	HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk

#define	HRTIM_ADC2R_AD2TCPER_Pos (21U)

#define	HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)

#define	HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk

#define	HRTIM_ADC2R_AD2TCRST_Pos (22U)

#define	HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)

#define	HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk

#define	HRTIM_ADC2R_AD2TDC2_Pos (23U)

#define	HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)

#define	HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk

#define	HRTIM_ADC2R_AD2TDC3_Pos (24U)

#define	HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)

#define	HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk

#define	HRTIM_ADC2R_AD2TDC4_Pos (25U)

#define	HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)

#define	HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk

#define	HRTIM_ADC2R_AD2TDPER_Pos (26U)

#define	HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)

#define	HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk

#define	HRTIM_ADC2R_AD2TDRST_Pos (27U)

#define	HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)

#define	HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk

#define	HRTIM_ADC2R_AD2TEC2_Pos (28U)

#define	HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)

#define	HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk

#define	HRTIM_ADC2R_AD2TEC3_Pos (29U)

#define	HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)

#define	HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk

#define	HRTIM_ADC2R_AD2TEC4_Pos (30U)

#define	HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)

#define	HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk

#define	HRTIM_ADC2R_AD2TERST_Pos (31U)

#define	HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)

#define	HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk

#define	HRTIM_ADC3R_AD3MC1_Pos (0U)

#define	HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)

#define	HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk

#define	HRTIM_ADC3R_AD3MC2_Pos (1U)

#define	HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)

#define	HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk

#define	HRTIM_ADC3R_AD3MC3_Pos (2U)

#define	HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)

#define	HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk

#define	HRTIM_ADC3R_AD3MC4_Pos (3U)

#define	HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)

#define	HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk

#define	HRTIM_ADC3R_AD3MPER_Pos (4U)

#define	HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)

#define	HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk

#define	HRTIM_ADC3R_AD3EEV1_Pos (5U)

#define	HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)

#define	HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk

#define	HRTIM_ADC3R_AD3EEV2_Pos (6U)

#define	HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)

#define	HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk

#define	HRTIM_ADC3R_AD3EEV3_Pos (7U)

#define	HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)

#define	HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk

#define	HRTIM_ADC3R_AD3EEV4_Pos (8U)

#define	HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)

#define	HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk

#define	HRTIM_ADC3R_AD3EEV5_Pos (9U)

#define	HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)

#define	HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk

#define	HRTIM_ADC3R_AD3TAC2_Pos (10U)

#define	HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)

#define	HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk

#define	HRTIM_ADC3R_AD3TAC3_Pos (11U)

#define	HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)

#define	HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk

#define	HRTIM_ADC3R_AD3TAC4_Pos (12U)

#define	HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)

#define	HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk

#define	HRTIM_ADC3R_AD3TAPER_Pos (13U)

#define	HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)

#define	HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk

#define	HRTIM_ADC3R_AD3TARST_Pos (14U)

#define	HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)

#define	HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk

#define	HRTIM_ADC3R_AD3TBC2_Pos (15U)

#define	HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)

#define	HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk

#define	HRTIM_ADC3R_AD3TBC3_Pos (16U)

#define	HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)

#define	HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk

#define	HRTIM_ADC3R_AD3TBC4_Pos (17U)

#define	HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)

#define	HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk

#define	HRTIM_ADC3R_AD3TBPER_Pos (18U)

#define	HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)

#define	HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk

#define	HRTIM_ADC3R_AD3TBRST_Pos (19U)

#define	HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)

#define	HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk

#define	HRTIM_ADC3R_AD3TCC2_Pos (20U)

#define	HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)

#define	HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk

#define	HRTIM_ADC3R_AD3TCC3_Pos (21U)

#define	HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)

#define	HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk

#define	HRTIM_ADC3R_AD3TCC4_Pos (22U)

#define	HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)

#define	HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk

#define	HRTIM_ADC3R_AD3TCPER_Pos (23U)

#define	HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)

#define	HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk

#define	HRTIM_ADC3R_AD3TDC2_Pos (24U)

#define	HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)

#define	HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk

#define	HRTIM_ADC3R_AD3TDC3_Pos (25U)

#define	HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)

#define	HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk

#define	HRTIM_ADC3R_AD3TDC4_Pos (26U)

#define	HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)

#define	HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk

#define	HRTIM_ADC3R_AD3TDPER_Pos (27U)

#define	HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)

#define	HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk

#define	HRTIM_ADC3R_AD3TEC2_Pos (28U)

#define	HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)

#define	HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk

#define	HRTIM_ADC3R_AD3TEC3_Pos (29U)

#define	HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)

#define	HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk

#define	HRTIM_ADC3R_AD3TEC4_Pos (30U)

#define	HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)

#define	HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk

#define	HRTIM_ADC3R_AD3TEPER_Pos (31U)

#define	HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)

#define	HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk

#define	HRTIM_ADC4R_AD4MC1_Pos (0U)

#define	HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)

#define	HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk

#define	HRTIM_ADC4R_AD4MC2_Pos (1U)

#define	HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)

#define	HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk

#define	HRTIM_ADC4R_AD4MC3_Pos (2U)

#define	HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)

#define	HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk

#define	HRTIM_ADC4R_AD4MC4_Pos (3U)

#define	HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)

#define	HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk

#define	HRTIM_ADC4R_AD4MPER_Pos (4U)

#define	HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)

#define	HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk

#define	HRTIM_ADC4R_AD4EEV6_Pos (5U)

#define	HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)

#define	HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk

#define	HRTIM_ADC4R_AD4EEV7_Pos (6U)

#define	HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)

#define	HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk

#define	HRTIM_ADC4R_AD4EEV8_Pos (7U)

#define	HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)

#define	HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk

#define	HRTIM_ADC4R_AD4EEV9_Pos (8U)

#define	HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)

#define	HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk

#define	HRTIM_ADC4R_AD4EEV10_Pos (9U)

#define	HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)

#define	HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk

#define	HRTIM_ADC4R_AD4TAC2_Pos (10U)

#define	HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)

#define	HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk

#define	HRTIM_ADC4R_AD4TAC3_Pos (11U)

#define	HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)

#define	HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk

#define	HRTIM_ADC4R_AD4TAC4_Pos (12U)

#define	HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)

#define	HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk

#define	HRTIM_ADC4R_AD4TAPER_Pos (13U)

#define	HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)

#define	HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk

#define	HRTIM_ADC4R_AD4TBC2_Pos (14U)

#define	HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)

#define	HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk

#define	HRTIM_ADC4R_AD4TBC3_Pos (15U)

#define	HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)

#define	HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk

#define	HRTIM_ADC4R_AD4TBC4_Pos (16U)

#define	HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)

#define	HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk

#define	HRTIM_ADC4R_AD4TBPER_Pos (17U)

#define	HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)

#define	HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk

#define	HRTIM_ADC4R_AD4TCC2_Pos (18U)

#define	HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)

#define	HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk

#define	HRTIM_ADC4R_AD4TCC3_Pos (19U)

#define	HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)

#define	HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk

#define	HRTIM_ADC4R_AD4TCC4_Pos (20U)

#define	HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)

#define	HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk

#define	HRTIM_ADC4R_AD4TCPER_Pos (21U)

#define	HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)

#define	HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk

#define	HRTIM_ADC4R_AD4TCRST_Pos (22U)

#define	HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)

#define	HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk

#define	HRTIM_ADC4R_AD4TDC2_Pos (23U)

#define	HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)

#define	HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk

#define	HRTIM_ADC4R_AD4TDC3_Pos (24U)

#define	HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)

#define	HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk

#define	HRTIM_ADC4R_AD4TDC4_Pos (25U)

#define	HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)

#define	HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk

#define	HRTIM_ADC4R_AD4TDPER_Pos (26U)

#define	HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)

#define	HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk

#define	HRTIM_ADC4R_AD4TDRST_Pos (27U)

#define	HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)

#define	HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk

#define	HRTIM_ADC4R_AD4TEC2_Pos (28U)

#define	HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)

#define	HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk

#define	HRTIM_ADC4R_AD4TEC3_Pos (29U)

#define	HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)

#define	HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk

#define	HRTIM_ADC4R_AD4TEC4_Pos (30U)

#define	HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)

#define	HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk

#define	HRTIM_ADC4R_AD4TERST_Pos (31U)

#define	HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)

#define	HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk

#define	HRTIM_DLLCR_CAL_Pos (0U)

#define	HRTIM_DLLCR_CAL_Msk (0x1UL << HRTIM_DLLCR_CAL_Pos)

#define	HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk

#define	HRTIM_DLLCR_CALEN_Pos (1U)

#define	HRTIM_DLLCR_CALEN_Msk (0x1UL << HRTIM_DLLCR_CALEN_Pos)

#define	HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk

#define	HRTIM_DLLCR_CALRTE_Pos (2U)

#define	HRTIM_DLLCR_CALRTE_Msk (0x3UL << HRTIM_DLLCR_CALRTE_Pos)

#define	HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk

#define	HRTIM_DLLCR_CALRTE_0 (0x1UL << HRTIM_DLLCR_CALRTE_Pos)

#define	HRTIM_DLLCR_CALRTE_1 (0x2UL << HRTIM_DLLCR_CALRTE_Pos)

#define	HRTIM_FLTINR1_FLT1E_Pos (0U)

#define	HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)

#define	HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk

#define	HRTIM_FLTINR1_FLT1P_Pos (1U)

#define	HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)

#define	HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk

#define	HRTIM_FLTINR1_FLT1SRC_Pos (2U)

#define	HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)

#define	HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk

#define	HRTIM_FLTINR1_FLT1F_Pos (3U)

#define	HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)

#define	HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk

#define	HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)

#define	HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)

#define	HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)

#define	HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)

#define	HRTIM_FLTINR1_FLT1LCK_Pos (7U)

#define	HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)

#define	HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk

#define	HRTIM_FLTINR1_FLT2E_Pos (8U)

#define	HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)

#define	HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk

#define	HRTIM_FLTINR1_FLT2P_Pos (9U)

#define	HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)

#define	HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk

#define	HRTIM_FLTINR1_FLT2SRC_Pos (10U)

#define	HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)

#define	HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk

#define	HRTIM_FLTINR1_FLT2F_Pos (11U)

#define	HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)

#define	HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk

#define	HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)

#define	HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)

#define	HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)

#define	HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)

#define	HRTIM_FLTINR1_FLT2LCK_Pos (15U)

#define	HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)

#define	HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk

#define	HRTIM_FLTINR1_FLT3E_Pos (16U)

#define	HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)

#define	HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk

#define	HRTIM_FLTINR1_FLT3P_Pos (17U)

#define	HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)

#define	HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk

#define	HRTIM_FLTINR1_FLT3SRC_Pos (18U)

#define	HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)

#define	HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk

#define	HRTIM_FLTINR1_FLT3F_Pos (19U)

#define	HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)

#define	HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk

#define	HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)

#define	HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)

#define	HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)

#define	HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)

#define	HRTIM_FLTINR1_FLT3LCK_Pos (23U)

#define	HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)

#define	HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk

#define	HRTIM_FLTINR1_FLT4E_Pos (24U)

#define	HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)

#define	HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk

#define	HRTIM_FLTINR1_FLT4P_Pos (25U)

#define	HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)

#define	HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk

#define	HRTIM_FLTINR1_FLT4SRC_Pos (26U)

#define	HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)

#define	HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk

#define	HRTIM_FLTINR1_FLT4F_Pos (27U)

#define	HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)

#define	HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk

#define	HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)

#define	HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)

#define	HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)

#define	HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)

#define	HRTIM_FLTINR1_FLT4LCK_Pos (31U)

#define	HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)

#define	HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk

#define	HRTIM_FLTINR2_FLT5E_Pos (0U)

#define	HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)

#define	HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk

#define	HRTIM_FLTINR2_FLT5P_Pos (1U)

#define	HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)

#define	HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk

#define	HRTIM_FLTINR2_FLT5SRC_Pos (2U)

#define	HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)

#define	HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk

#define	HRTIM_FLTINR2_FLT5F_Pos (3U)

#define	HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)

#define	HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk

#define	HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)

#define	HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)

#define	HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)

#define	HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)

#define	HRTIM_FLTINR2_FLT5LCK_Pos (7U)

#define	HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)

#define	HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk

#define	HRTIM_FLTINR2_FLTSD_Pos (24U)

#define	HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)

#define	HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk

#define	HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)

#define	HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)

#define	HRTIM_BDMUPR_MCR_Pos (0U)

#define	HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos)

#define	HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk

#define	HRTIM_BDMUPR_MICR_Pos (1U)

#define	HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos)

#define	HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk

#define	HRTIM_BDMUPR_MDIER_Pos (2U)

#define	HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos)

#define	HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk

#define	HRTIM_BDMUPR_MCNT_Pos (3U)

#define	HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos)

#define	HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk

#define	HRTIM_BDMUPR_MPER_Pos (4U)

#define	HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos)

#define	HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk

#define	HRTIM_BDMUPR_MREP_Pos (5U)

#define	HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos)

#define	HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk

#define	HRTIM_BDMUPR_MCMP1_Pos (6U)

#define	HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)

#define	HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk

#define	HRTIM_BDMUPR_MCMP2_Pos (7U)

#define	HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)

#define	HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk

#define	HRTIM_BDMUPR_MCMP3_Pos (8U)

#define	HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)

#define	HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk

#define	HRTIM_BDMUPR_MCMP4_Pos (9U)

#define	HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)

#define	HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk

#define	HRTIM_BDTUPR_TIMCR_Pos (0U)

#define	HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)

#define	HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk

#define	HRTIM_BDTUPR_TIMICR_Pos (1U)

#define	HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)

#define	HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk

#define	HRTIM_BDTUPR_TIMDIER_Pos (2U)

#define	HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)

#define	HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk

#define	HRTIM_BDTUPR_TIMCNT_Pos (3U)

#define	HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)

#define	HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk

#define	HRTIM_BDTUPR_TIMPER_Pos (4U)

#define	HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)

#define	HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk

#define	HRTIM_BDTUPR_TIMREP_Pos (5U)

#define	HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)

#define	HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk

#define	HRTIM_BDTUPR_TIMCMP1_Pos (6U)

#define	HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)

#define	HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk

#define	HRTIM_BDTUPR_TIMCMP2_Pos (7U)

#define	HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)

#define	HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk

#define	HRTIM_BDTUPR_TIMCMP3_Pos (8U)

#define	HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)

#define	HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk

#define	HRTIM_BDTUPR_TIMCMP4_Pos (9U)

#define	HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)

#define	HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk

#define	HRTIM_BDTUPR_TIMDTR_Pos (10U)

#define	HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)

#define	HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk

#define	HRTIM_BDTUPR_TIMSET1R_Pos (11U)

#define	HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)

#define	HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk

#define	HRTIM_BDTUPR_TIMRST1R_Pos (12U)

#define	HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)

#define	HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk

#define	HRTIM_BDTUPR_TIMSET2R_Pos (13U)

#define	HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)

#define	HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk

#define	HRTIM_BDTUPR_TIMRST2R_Pos (14U)

#define	HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)

#define	HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk

#define	HRTIM_BDTUPR_TIMEEFR1_Pos (15U)

#define	HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)

#define	HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk

#define	HRTIM_BDTUPR_TIMEEFR2_Pos (16U)

#define	HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)

#define	HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk

#define	HRTIM_BDTUPR_TIMRSTR_Pos (17U)

#define	HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)

#define	HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk

#define	HRTIM_BDTUPR_TIMCHPR_Pos (18U)

#define	HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)

#define	HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk

#define	HRTIM_BDTUPR_TIMOUTR_Pos (19U)

#define	HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)

#define	HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk

#define	HRTIM_BDTUPR_TIMFLTR_Pos (20U)

#define	HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)

#define	HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk

#define	HRTIM_BDMADR_BDMADR_Pos (0U)

#define	HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)

#define	HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_TXIE_Pos (1U)

#define	I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

#define	I2C_CR1_TXIE I2C_CR1_TXIE_Msk

#define	I2C_CR1_RXIE_Pos (2U)

#define	I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

#define	I2C_CR1_RXIE I2C_CR1_RXIE_Msk

#define	I2C_CR1_ADDRIE_Pos (3U)

#define	I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

#define	I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

#define	I2C_CR1_NACKIE_Pos (4U)

#define	I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

#define	I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

#define	I2C_CR1_STOPIE_Pos (5U)

#define	I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

#define	I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

#define	I2C_CR1_TCIE_Pos (6U)

#define	I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

#define	I2C_CR1_TCIE I2C_CR1_TCIE_Msk

#define	I2C_CR1_ERRIE_Pos (7U)

#define	I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

#define	I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

#define	I2C_CR1_DNF_Pos (8U)

#define	I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

#define	I2C_CR1_DNF I2C_CR1_DNF_Msk

#define	I2C_CR1_ANFOFF_Pos (12U)

#define	I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

#define	I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

#define	I2C_CR1_SWRST_Pos (13U)

#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk

#define	I2C_CR1_TXDMAEN_Pos (14U)

#define	I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

#define	I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

#define	I2C_CR1_RXDMAEN_Pos (15U)

#define	I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

#define	I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

#define	I2C_CR1_SBC_Pos (16U)

#define	I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

#define	I2C_CR1_SBC I2C_CR1_SBC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (17U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_WUPEN_Pos (18U)

#define	I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

#define	I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

#define	I2C_CR1_GCEN_Pos (19U)

#define	I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

#define	I2C_CR1_GCEN I2C_CR1_GCEN_Msk

#define	I2C_CR1_SMBHEN_Pos (20U)

#define	I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

#define	I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

#define	I2C_CR1_SMBDEN_Pos (21U)

#define	I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

#define	I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

#define	I2C_CR1_ALERTEN_Pos (22U)

#define	I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

#define	I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

#define	I2C_CR1_PECEN_Pos (23U)

#define	I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

#define	I2C_CR1_PECEN I2C_CR1_PECEN_Msk

#define	I2C_CR1_DFN I2C_CR1_DNF

#define	I2C_CR2_SADD_Pos (0U)

#define	I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

#define	I2C_CR2_SADD I2C_CR2_SADD_Msk

#define	I2C_CR2_RD_WRN_Pos (10U)

#define	I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

#define	I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

#define	I2C_CR2_ADD10_Pos (11U)

#define	I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

#define	I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

#define	I2C_CR2_HEAD10R_Pos (12U)

#define	I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

#define	I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

#define	I2C_CR2_START_Pos (13U)

#define	I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

#define	I2C_CR2_START I2C_CR2_START_Msk

#define	I2C_CR2_STOP_Pos (14U)

#define	I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

#define	I2C_CR2_STOP I2C_CR2_STOP_Msk

#define	I2C_CR2_NACK_Pos (15U)

#define	I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

#define	I2C_CR2_NACK I2C_CR2_NACK_Msk

#define	I2C_CR2_NBYTES_Pos (16U)

#define	I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

#define	I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

#define	I2C_CR2_RELOAD_Pos (24U)

#define	I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

#define	I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

#define	I2C_CR2_AUTOEND_Pos (25U)

#define	I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

#define	I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

#define	I2C_CR2_PECBYTE_Pos (26U)

#define	I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

#define	I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

#define	I2C_OAR1_OA1_Pos (0U)

#define	I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

#define	I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

#define	I2C_OAR1_OA1MODE_Pos (10U)

#define	I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

#define	I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

#define	I2C_OAR1_OA1EN_Pos (15U)

#define	I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

#define	I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

#define	I2C_OAR2_OA2_Pos (1U)

#define	I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

#define	I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

#define	I2C_OAR2_OA2MSK_Pos (8U)

#define	I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

#define	I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

#define	I2C_OAR2_OA2NOMASK (0x00000000U)

#define	I2C_OAR2_OA2MASK01_Pos (8U)

#define	I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

#define	I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

#define	I2C_OAR2_OA2MASK02_Pos (9U)

#define	I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

#define	I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

#define	I2C_OAR2_OA2MASK03_Pos (8U)

#define	I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

#define	I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

#define	I2C_OAR2_OA2MASK04_Pos (10U)

#define	I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

#define	I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

#define	I2C_OAR2_OA2MASK05_Pos (8U)

#define	I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

#define	I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

#define	I2C_OAR2_OA2MASK06_Pos (9U)

#define	I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

#define	I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

#define	I2C_OAR2_OA2MASK07_Pos (8U)

#define	I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

#define	I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

#define	I2C_OAR2_OA2EN_Pos (15U)

#define	I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

#define	I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

#define	I2C_TIMINGR_SCLL_Pos (0U)

#define	I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

#define	I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

#define	I2C_TIMINGR_SCLH_Pos (8U)

#define	I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

#define	I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

#define	I2C_TIMINGR_SDADEL_Pos (16U)

#define	I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

#define	I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

#define	I2C_TIMINGR_SCLDEL_Pos (20U)

#define	I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

#define	I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

#define	I2C_TIMINGR_PRESC_Pos (28U)

#define	I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

#define	I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

#define	I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

#define	I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

#define	I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

#define	I2C_TIMEOUTR_TIDLE_Pos (12U)

#define	I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

#define	I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

#define	I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

#define	I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

#define	I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

#define	I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

#define	I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

#define	I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

#define	I2C_TIMEOUTR_TEXTEN_Pos (31U)

#define	I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

#define	I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

#define	I2C_ISR_TXE_Pos (0U)

#define	I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

#define	I2C_ISR_TXE I2C_ISR_TXE_Msk

#define	I2C_ISR_TXIS_Pos (1U)

#define	I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

#define	I2C_ISR_TXIS I2C_ISR_TXIS_Msk

#define	I2C_ISR_RXNE_Pos (2U)

#define	I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

#define	I2C_ISR_RXNE I2C_ISR_RXNE_Msk

#define	I2C_ISR_ADDR_Pos (3U)

#define	I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

#define	I2C_ISR_ADDR I2C_ISR_ADDR_Msk

#define	I2C_ISR_NACKF_Pos (4U)

#define	I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

#define	I2C_ISR_NACKF I2C_ISR_NACKF_Msk

#define	I2C_ISR_STOPF_Pos (5U)

#define	I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

#define	I2C_ISR_STOPF I2C_ISR_STOPF_Msk

#define	I2C_ISR_TC_Pos (6U)

#define	I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

#define	I2C_ISR_TC I2C_ISR_TC_Msk

#define	I2C_ISR_TCR_Pos (7U)

#define	I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

#define	I2C_ISR_TCR I2C_ISR_TCR_Msk

#define	I2C_ISR_BERR_Pos (8U)

#define	I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

#define	I2C_ISR_BERR I2C_ISR_BERR_Msk

#define	I2C_ISR_ARLO_Pos (9U)

#define	I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

#define	I2C_ISR_ARLO I2C_ISR_ARLO_Msk

#define	I2C_ISR_OVR_Pos (10U)

#define	I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

#define	I2C_ISR_OVR I2C_ISR_OVR_Msk

#define	I2C_ISR_PECERR_Pos (11U)

#define	I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

#define	I2C_ISR_PECERR I2C_ISR_PECERR_Msk

#define	I2C_ISR_TIMEOUT_Pos (12U)

#define	I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

#define	I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

#define	I2C_ISR_ALERT_Pos (13U)

#define	I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

#define	I2C_ISR_ALERT I2C_ISR_ALERT_Msk

#define	I2C_ISR_BUSY_Pos (15U)

#define	I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

#define	I2C_ISR_BUSY I2C_ISR_BUSY_Msk

#define	I2C_ISR_DIR_Pos (16U)

#define	I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

#define	I2C_ISR_DIR I2C_ISR_DIR_Msk

#define	I2C_ISR_ADDCODE_Pos (17U)

#define	I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

#define	I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

#define	I2C_ICR_ADDRCF_Pos (3U)

#define	I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

#define	I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

#define	I2C_ICR_NACKCF_Pos (4U)

#define	I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

#define	I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

#define	I2C_ICR_STOPCF_Pos (5U)

#define	I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

#define	I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

#define	I2C_ICR_BERRCF_Pos (8U)

#define	I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

#define	I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

#define	I2C_ICR_ARLOCF_Pos (9U)

#define	I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

#define	I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

#define	I2C_ICR_OVRCF_Pos (10U)

#define	I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

#define	I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

#define	I2C_ICR_PECCF_Pos (11U)

#define	I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

#define	I2C_ICR_PECCF I2C_ICR_PECCF_Msk

#define	I2C_ICR_TIMOUTCF_Pos (12U)

#define	I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

#define	I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

#define	I2C_ICR_ALERTCF_Pos (13U)

#define	I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

#define	I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

#define	I2C_PECR_PEC_Pos (0U)

#define	I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

#define	I2C_PECR_PEC I2C_PECR_PEC_Msk

#define	I2C_RXDR_RXDATA_Pos (0U)

#define	I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

#define	I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

#define	I2C_TXDR_TXDATA_Pos (0U)

#define	I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

#define	I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	IWDG_SR_WVU_Pos (2U)

#define	IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

#define	IWDG_SR_WVU IWDG_SR_WVU_Msk

#define	IWDG_WINR_WIN_Pos (0U)

#define	IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

#define	IWDG_WINR_WIN IWDG_WINR_WIN_Msk

#define	PWR_PVD_SUPPORT

#define	PWR_CR_LPDS_Pos (0U)

#define	PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)

#define	PWR_CR_LPDS PWR_CR_LPDS_Msk

#define	PWR_CR_PDDS_Pos (1U)

#define	PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)

#define	PWR_CR_PDDS PWR_CR_PDDS_Msk

#define	PWR_CR_CWUF_Pos (2U)

#define	PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)

#define	PWR_CR_CWUF PWR_CR_CWUF_Msk

#define	PWR_CR_CSBF_Pos (3U)

#define	PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)

#define	PWR_CR_CSBF PWR_CR_CSBF_Msk

#define	PWR_CR_PVDE_Pos (4U)

#define	PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)

#define	PWR_CR_PVDE PWR_CR_PVDE_Msk

#define	PWR_CR_PLS_Pos (5U)

#define	PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS PWR_CR_PLS_Msk

#define	PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_LEV0 (0x00000000U)

#define	PWR_CR_PLS_LEV1 (0x00000020U)

#define	PWR_CR_PLS_LEV2 (0x00000040U)

#define	PWR_CR_PLS_LEV3 (0x00000060U)

#define	PWR_CR_PLS_LEV4 (0x00000080U)

#define	PWR_CR_PLS_LEV5 (0x000000A0U)

#define	PWR_CR_PLS_LEV6 (0x000000C0U)

#define	PWR_CR_PLS_LEV7 (0x000000E0U)

#define	PWR_CR_DBP_Pos (8U)

#define	PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)

#define	PWR_CR_DBP PWR_CR_DBP_Msk

#define	PWR_CSR_WUF_Pos (0U)

#define	PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)

#define	PWR_CSR_WUF PWR_CSR_WUF_Msk

#define	PWR_CSR_SBF_Pos (1U)

#define	PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)

#define	PWR_CSR_SBF PWR_CSR_SBF_Msk

#define	PWR_CSR_PVDO_Pos (2U)

#define	PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)

#define	PWR_CSR_PVDO PWR_CSR_PVDO_Msk

#define	PWR_CSR_EWUP1_Pos (8U)

#define	PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)

#define	PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk

#define	PWR_CSR_EWUP2_Pos (9U)

#define	PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)

#define	PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk

#define	PWR_CSR_EWUP3_Pos (10U)

#define	PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)

#define	PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk

#define	RCC_CR_HSION_Pos (0U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIRDY_Pos (1U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSITRIM_Pos (3U)

#define	RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk

#define	RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSICAL_Pos (8U)

#define	RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL RCC_CR_HSICAL_Msk

#define	RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_HSEBYP_Pos (18U)

#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_HSI (0x00000000U)

#define	RCC_CFGR_SW_HSE (0x00000001U)

#define	RCC_CFGR_SW_PLL (0x00000002U)

#define	RCC_CFGR_SWS_Pos (2U)

#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_HSI (0x00000000U)

#define	RCC_CFGR_SWS_HSE (0x00000004U)

#define	RCC_CFGR_SWS_PLL (0x00000008U)

#define	RCC_CFGR_HPRE_Pos (4U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_HPRE_DIV2 (0x00000080U)

#define	RCC_CFGR_HPRE_DIV4 (0x00000090U)

#define	RCC_CFGR_HPRE_DIV8 (0x000000A0U)

#define	RCC_CFGR_HPRE_DIV16 (0x000000B0U)

#define	RCC_CFGR_HPRE_DIV64 (0x000000C0U)

#define	RCC_CFGR_HPRE_DIV128 (0x000000D0U)

#define	RCC_CFGR_HPRE_DIV256 (0x000000E0U)

#define	RCC_CFGR_HPRE_DIV512 (0x000000F0U)

#define	RCC_CFGR_PPRE1_Pos (8U)

#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE1_DIV2 (0x00000400U)

#define	RCC_CFGR_PPRE1_DIV4 (0x00000500U)

#define	RCC_CFGR_PPRE1_DIV8 (0x00000600U)

#define	RCC_CFGR_PPRE1_DIV16 (0x00000700U)

#define	RCC_CFGR_PPRE2_Pos (11U)

#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE2_DIV2 (0x00002000U)

#define	RCC_CFGR_PPRE2_DIV4 (0x00002800U)

#define	RCC_CFGR_PPRE2_DIV8 (0x00003000U)

#define	RCC_CFGR_PPRE2_DIV16 (0x00003800U)

#define	RCC_CFGR_PLLSRC_Pos (16U)

#define	RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)

#define	RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk

#define	RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U)

#define	RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U)

#define	RCC_CFGR_PLLXTPRE_Pos (17U)

#define	RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)

#define	RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk

#define	RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U)

#define	RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U)

#define	RCC_CFGR_PLLMUL_Pos (18U)

#define	RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk

#define	RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL2 (0x00000000U)

#define	RCC_CFGR_PLLMUL3 (0x00040000U)

#define	RCC_CFGR_PLLMUL4 (0x00080000U)

#define	RCC_CFGR_PLLMUL5 (0x000C0000U)

#define	RCC_CFGR_PLLMUL6 (0x00100000U)

#define	RCC_CFGR_PLLMUL7 (0x00140000U)

#define	RCC_CFGR_PLLMUL8 (0x00180000U)

#define	RCC_CFGR_PLLMUL9 (0x001C0000U)

#define	RCC_CFGR_PLLMUL10 (0x00200000U)

#define	RCC_CFGR_PLLMUL11 (0x00240000U)

#define	RCC_CFGR_PLLMUL12 (0x00280000U)

#define	RCC_CFGR_PLLMUL13 (0x002C0000U)

#define	RCC_CFGR_PLLMUL14 (0x00300000U)

#define	RCC_CFGR_PLLMUL15 (0x00340000U)

#define	RCC_CFGR_PLLMUL16 (0x00380000U)

#define	RCC_CFGR_MCO_Pos (24U)

#define	RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO RCC_CFGR_MCO_Msk

#define	RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_NOCLOCK (0x00000000U)

#define	RCC_CFGR_MCO_LSI (0x02000000U)

#define	RCC_CFGR_MCO_LSE (0x03000000U)

#define	RCC_CFGR_MCO_SYSCLK (0x04000000U)

#define	RCC_CFGR_MCO_HSI (0x05000000U)

#define	RCC_CFGR_MCO_HSE (0x06000000U)

#define	RCC_CFGR_MCO_PLL (0x07000000U)

#define	RCC_CFGR_MCOPRE_Pos (28U)

#define	RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

#define	RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_MCOPRE_DIV2 (0x10000000U)

#define	RCC_CFGR_MCOPRE_DIV4 (0x20000000U)

#define	RCC_CFGR_MCOPRE_DIV8 (0x30000000U)

#define	RCC_CFGR_MCOPRE_DIV16 (0x40000000U)

#define	RCC_CFGR_MCOPRE_DIV32 (0x50000000U)

#define	RCC_CFGR_MCOPRE_DIV64 (0x60000000U)

#define	RCC_CFGR_MCOPRE_DIV128 (0x70000000U)

#define	RCC_CFGR_PLLNODIV_Pos (31U)

#define	RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos)

#define	RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCO

#define	RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0

#define	RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1

#define	RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2

#define	RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK

#define	RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI

#define	RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE

#define	RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK

#define	RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI

#define	RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE

#define	RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL

#define	RCC_CIR_LSIRDYF_Pos (0U)

#define	RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)

#define	RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk

#define	RCC_CIR_LSERDYF_Pos (1U)

#define	RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)

#define	RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk

#define	RCC_CIR_HSIRDYF_Pos (2U)

#define	RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)

#define	RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk

#define	RCC_CIR_HSERDYF_Pos (3U)

#define	RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)

#define	RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk

#define	RCC_CIR_PLLRDYF_Pos (4U)

#define	RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)

#define	RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk

#define	RCC_CIR_CSSF_Pos (7U)

#define	RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)

#define	RCC_CIR_CSSF RCC_CIR_CSSF_Msk

#define	RCC_CIR_LSIRDYIE_Pos (8U)

#define	RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)

#define	RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk

#define	RCC_CIR_LSERDYIE_Pos (9U)

#define	RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)

#define	RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk

#define	RCC_CIR_HSIRDYIE_Pos (10U)

#define	RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)

#define	RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk

#define	RCC_CIR_HSERDYIE_Pos (11U)

#define	RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)

#define	RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk

#define	RCC_CIR_PLLRDYIE_Pos (12U)

#define	RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)

#define	RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk

#define	RCC_CIR_LSIRDYC_Pos (16U)

#define	RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)

#define	RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk

#define	RCC_CIR_LSERDYC_Pos (17U)

#define	RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)

#define	RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk

#define	RCC_CIR_HSIRDYC_Pos (18U)

#define	RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)

#define	RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk

#define	RCC_CIR_HSERDYC_Pos (19U)

#define	RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)

#define	RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk

#define	RCC_CIR_PLLRDYC_Pos (20U)

#define	RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)

#define	RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk

#define	RCC_CIR_CSSC_Pos (23U)

#define	RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)

#define	RCC_CIR_CSSC RCC_CIR_CSSC_Msk

#define	RCC_APB2RSTR_SYSCFGRST_Pos (0U)

#define	RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

#define	RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk

#define	RCC_APB2RSTR_TIM1RST_Pos (11U)

#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

#define	RCC_APB2RSTR_SPI1RST_Pos (12U)

#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

#define	RCC_APB2RSTR_USART1RST_Pos (14U)

#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

#define	RCC_APB2RSTR_TIM15RST_Pos (16U)

#define	RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)

#define	RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk

#define	RCC_APB2RSTR_TIM16RST_Pos (17U)

#define	RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)

#define	RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

#define	RCC_APB2RSTR_TIM17RST_Pos (18U)

#define	RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)

#define	RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

#define	RCC_APB2RSTR_HRTIM1RST_Pos (29U)

#define	RCC_APB2RSTR_HRTIM1RST_Msk (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)

#define	RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk

#define	RCC_APB1RSTR_TIM2RST_Pos (0U)

#define	RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)

#define	RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk

#define	RCC_APB1RSTR_TIM3RST_Pos (1U)

#define	RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)

#define	RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk

#define	RCC_APB1RSTR_TIM6RST_Pos (4U)

#define	RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)

#define	RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk

#define	RCC_APB1RSTR_TIM7RST_Pos (5U)

#define	RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)

#define	RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk

#define	RCC_APB1RSTR_WWDGRST_Pos (11U)

#define	RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)

#define	RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk

#define	RCC_APB1RSTR_USART2RST_Pos (17U)

#define	RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)

#define	RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk

#define	RCC_APB1RSTR_USART3RST_Pos (18U)

#define	RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)

#define	RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk

#define	RCC_APB1RSTR_I2C1RST_Pos (21U)

#define	RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)

#define	RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk

#define	RCC_APB1RSTR_CANRST_Pos (25U)

#define	RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos)

#define	RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk

#define	RCC_APB1RSTR_DAC2RST_Pos (26U)

#define	RCC_APB1RSTR_DAC2RST_Msk (0x1UL << RCC_APB1RSTR_DAC2RST_Pos)

#define	RCC_APB1RSTR_DAC2RST RCC_APB1RSTR_DAC2RST_Msk

#define	RCC_APB1RSTR_PWRRST_Pos (28U)

#define	RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)

#define	RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk

#define	RCC_APB1RSTR_DAC1RST_Pos (29U)

#define	RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos)

#define	RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk

#define	RCC_AHBENR_DMA1EN_Pos (0U)

#define	RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

#define	RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

#define	RCC_AHBENR_SRAMEN_Pos (2U)

#define	RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)

#define	RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk

#define	RCC_AHBENR_FLITFEN_Pos (4U)

#define	RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)

#define	RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk

#define	RCC_AHBENR_CRCEN_Pos (6U)

#define	RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

#define	RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

#define	RCC_AHBENR_GPIOAEN_Pos (17U)

#define	RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)

#define	RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk

#define	RCC_AHBENR_GPIOBEN_Pos (18U)

#define	RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)

#define	RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk

#define	RCC_AHBENR_GPIOCEN_Pos (19U)

#define	RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)

#define	RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk

#define	RCC_AHBENR_GPIODEN_Pos (20U)

#define	RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos)

#define	RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk

#define	RCC_AHBENR_GPIOFEN_Pos (22U)

#define	RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)

#define	RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk

#define	RCC_AHBENR_TSCEN_Pos (24U)

#define	RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos)

#define	RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk

#define	RCC_AHBENR_ADC12EN_Pos (28U)

#define	RCC_AHBENR_ADC12EN_Msk (0x1UL << RCC_AHBENR_ADC12EN_Pos)

#define	RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk

#define	RCC_APB2ENR_SYSCFGEN_Pos (0U)

#define	RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

#define	RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk

#define	RCC_APB2ENR_TIM1EN_Pos (11U)

#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

#define	RCC_APB2ENR_SPI1EN_Pos (12U)

#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

#define	RCC_APB2ENR_USART1EN_Pos (14U)

#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

#define	RCC_APB2ENR_TIM15EN_Pos (16U)

#define	RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)

#define	RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk

#define	RCC_APB2ENR_TIM16EN_Pos (17U)

#define	RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

#define	RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

#define	RCC_APB2ENR_TIM17EN_Pos (18U)

#define	RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

#define	RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

#define	RCC_APB2ENR_HRTIM1EN_Pos (29U)

#define	RCC_APB2ENR_HRTIM1EN_Msk (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)

#define	RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk

#define	RCC_APB1ENR_TIM2EN_Pos (0U)

#define	RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)

#define	RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk

#define	RCC_APB1ENR_TIM3EN_Pos (1U)

#define	RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)

#define	RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk

#define	RCC_APB1ENR_TIM6EN_Pos (4U)

#define	RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)

#define	RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk

#define	RCC_APB1ENR_TIM7EN_Pos (5U)

#define	RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)

#define	RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk

#define	RCC_APB1ENR_WWDGEN_Pos (11U)

#define	RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)

#define	RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk

#define	RCC_APB1ENR_USART2EN_Pos (17U)

#define	RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)

#define	RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk

#define	RCC_APB1ENR_USART3EN_Pos (18U)

#define	RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)

#define	RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk

#define	RCC_APB1ENR_I2C1EN_Pos (21U)

#define	RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)

#define	RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk

#define	RCC_APB1ENR_CANEN_Pos (25U)

#define	RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos)

#define	RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk

#define	RCC_APB1ENR_DAC2EN_Pos (26U)

#define	RCC_APB1ENR_DAC2EN_Msk (0x1UL << RCC_APB1ENR_DAC2EN_Pos)

#define	RCC_APB1ENR_DAC2EN RCC_APB1ENR_DAC2EN_Msk

#define	RCC_APB1ENR_PWREN_Pos (28U)

#define	RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)

#define	RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk

#define	RCC_APB1ENR_DAC1EN_Pos (29U)

#define	RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos)

#define	RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk

#define	RCC_BDCR_LSE_Pos (0U)

#define	RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos)

#define	RCC_BDCR_LSE RCC_BDCR_LSE_Msk

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_LSEDRV_Pos (3U)

#define	RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

#define	RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U)

#define	RCC_BDCR_RTCSEL_LSE (0x00000100U)

#define	RCC_BDCR_RTCSEL_LSI (0x00000200U)

#define	RCC_BDCR_RTCSEL_HSE (0x00000300U)

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_V18PWRRSTF_Pos (23U)

#define	RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos)

#define	RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk

#define	RCC_CSR_RMVF_Pos (24U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_OBLRSTF_Pos (25U)

#define	RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

#define	RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_PORRSTF_Pos (27U)

#define	RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)

#define	RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RCC_AHBRSTR_GPIOARST_Pos (17U)

#define	RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos)

#define	RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk

#define	RCC_AHBRSTR_GPIOBRST_Pos (18U)

#define	RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos)

#define	RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk

#define	RCC_AHBRSTR_GPIOCRST_Pos (19U)

#define	RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos)

#define	RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk

#define	RCC_AHBRSTR_GPIODRST_Pos (20U)

#define	RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos)

#define	RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk

#define	RCC_AHBRSTR_GPIOFRST_Pos (22U)

#define	RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos)

#define	RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk

#define	RCC_AHBRSTR_TSCRST_Pos (24U)

#define	RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos)

#define	RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk

#define	RCC_AHBRSTR_ADC12RST_Pos (28U)

#define	RCC_AHBRSTR_ADC12RST_Msk (0x1UL << RCC_AHBRSTR_ADC12RST_Pos)

#define	RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk

#define	RCC_CFGR2_PREDIV_Pos (0U)

#define	RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk

#define	RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_DIV1 (0x00000000U)

#define	RCC_CFGR2_PREDIV_DIV2 (0x00000001U)

#define	RCC_CFGR2_PREDIV_DIV3 (0x00000002U)

#define	RCC_CFGR2_PREDIV_DIV4 (0x00000003U)

#define	RCC_CFGR2_PREDIV_DIV5 (0x00000004U)

#define	RCC_CFGR2_PREDIV_DIV6 (0x00000005U)

#define	RCC_CFGR2_PREDIV_DIV7 (0x00000006U)

#define	RCC_CFGR2_PREDIV_DIV8 (0x00000007U)

#define	RCC_CFGR2_PREDIV_DIV9 (0x00000008U)

#define	RCC_CFGR2_PREDIV_DIV10 (0x00000009U)

#define	RCC_CFGR2_PREDIV_DIV11 (0x0000000AU)

#define	RCC_CFGR2_PREDIV_DIV12 (0x0000000BU)

#define	RCC_CFGR2_PREDIV_DIV13 (0x0000000CU)

#define	RCC_CFGR2_PREDIV_DIV14 (0x0000000DU)

#define	RCC_CFGR2_PREDIV_DIV15 (0x0000000EU)

#define	RCC_CFGR2_PREDIV_DIV16 (0x0000000FU)

#define	RCC_CFGR2_ADCPRE12_Pos (4U)

#define	RCC_CFGR2_ADCPRE12_Msk (0x1FUL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk

#define	RCC_CFGR2_ADCPRE12_0 (0x01UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_1 (0x02UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_2 (0x04UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_3 (0x08UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_4 (0x10UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_NO (0x00000000U)

#define	RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U)

#define	RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U)

#define	RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U)

#define	RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U)

#define	RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U)

#define	RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U)

#define	RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U)

#define	RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U)

#define	RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U)

#define	RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U)

#define	RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U)

#define	RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U)

#define	RCC_CFGR3_USART1SW_Pos (0U)

#define	RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk

#define	RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW_PCLK1 (0x00000000U)

#define	RCC_CFGR3_USART1SW_SYSCLK (0x00000001U)

#define	RCC_CFGR3_USART1SW_LSE (0x00000002U)

#define	RCC_CFGR3_USART1SW_HSI (0x00000003U)

#define	RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1

#define	RCC_CFGR3_I2CSW_Pos (4U)

#define	RCC_CFGR3_I2CSW_Msk (0x1UL << RCC_CFGR3_I2CSW_Pos)

#define	RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk

#define	RCC_CFGR3_I2C1SW_Pos (4U)

#define	RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos)

#define	RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk

#define	RCC_CFGR3_I2C1SW_HSI (0x00000000U)

#define	RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)

#define	RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos)

#define	RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk

#define	RCC_CFGR3_TIMSW_Pos (8U)

#define	RCC_CFGR3_TIMSW_Msk (0x1UL << RCC_CFGR3_TIMSW_Pos)

#define	RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk

#define	RCC_CFGR3_TIM1SW_Pos (8U)

#define	RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos)

#define	RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk

#define	RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM1SW_PLL_Pos (8U)

#define	RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos)

#define	RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk

#define	RCC_CFGR3_HRTIMSW_Pos (12U)

#define	RCC_CFGR3_HRTIMSW_Msk (0x1UL << RCC_CFGR3_HRTIMSW_Pos)

#define	RCC_CFGR3_HRTIMSW RCC_CFGR3_HRTIMSW_Msk

#define	RCC_CFGR3_HRTIM1SW_Pos (12U)

#define	RCC_CFGR3_HRTIM1SW_Msk (0x1UL << RCC_CFGR3_HRTIM1SW_Pos)

#define	RCC_CFGR3_HRTIM1SW RCC_CFGR3_HRTIM1SW_Msk

#define	RCC_CFGR3_HRTIM1SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_HRTIM1SW_PLL_Pos (12U)

#define	RCC_CFGR3_HRTIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_HRTIM1SW_PLL_Pos)

#define	RCC_CFGR3_HRTIM1SW_PLL RCC_CFGR3_HRTIM1SW_PLL_Msk

#define	RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2

#define	RCC_CFGR3_HRTIM1SW_HCLK RCC_CFGR3_HRTIM1SW_PCLK2

#define	RTC_TAMPER1_SUPPORT

#define	RTC_TAMPER2_SUPPORT

#define	RTC_BACKUP_SUPPORT

#define	RTC_WAKEUP_SUPPORT

#define	RTC_TR_PM_Pos (22U)

#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

#define	RTC_TR_PM RTC_TR_PM_Msk

#define	RTC_TR_HT_Pos (20U)

#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT RTC_TR_HT_Msk

#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

#define	RTC_TR_HU_Pos (16U)

#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

#define	RTC_TR_HU RTC_TR_HU_Msk

#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

#define	RTC_TR_MNT_Pos (12U)

#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT RTC_TR_MNT_Msk

#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNU_Pos (8U)

#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU RTC_TR_MNU_Msk

#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

#define	RTC_TR_ST_Pos (4U)

#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST RTC_TR_ST_Msk

#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

#define	RTC_TR_SU_Pos (0U)

#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

#define	RTC_TR_SU RTC_TR_SU_Msk

#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

#define	RTC_DR_YT_Pos (20U)

#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

#define	RTC_DR_YT RTC_DR_YT_Msk

#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

#define	RTC_DR_YU_Pos (16U)

#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

#define	RTC_DR_YU RTC_DR_YU_Msk

#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

#define	RTC_DR_WDU_Pos (13U)

#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU RTC_DR_WDU_Msk

#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

#define	RTC_DR_MT_Pos (12U)

#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

#define	RTC_DR_MT RTC_DR_MT_Msk

#define	RTC_DR_MU_Pos (8U)

#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

#define	RTC_DR_MU RTC_DR_MU_Msk

#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

#define	RTC_DR_DT_Pos (4U)

#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT RTC_DR_DT_Msk

#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

#define	RTC_DR_DU_Pos (0U)

#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

#define	RTC_DR_DU RTC_DR_DU_Msk

#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

#define	RTC_CR_COE_Pos (23U)

#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

#define	RTC_CR_COE RTC_CR_COE_Msk

#define	RTC_CR_OSEL_Pos (21U)

#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL RTC_CR_OSEL_Msk

#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_POL_Pos (20U)

#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

#define	RTC_CR_POL RTC_CR_POL_Msk

#define	RTC_CR_COSEL_Pos (19U)

#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

#define	RTC_CR_COSEL RTC_CR_COSEL_Msk

#define	RTC_CR_BKP_Pos (18U)

#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

#define	RTC_CR_BKP RTC_CR_BKP_Msk

#define	RTC_CR_SUB1H_Pos (17U)

#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk

#define	RTC_CR_ADD1H_Pos (16U)

#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk

#define	RTC_CR_TSIE_Pos (15U)

#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

#define	RTC_CR_TSIE RTC_CR_TSIE_Msk

#define	RTC_CR_WUTIE_Pos (14U)

#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk

#define	RTC_CR_ALRBIE_Pos (13U)

#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

#define	RTC_CR_ALRAIE_Pos (12U)

#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

#define	RTC_CR_TSE_Pos (11U)

#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

#define	RTC_CR_TSE RTC_CR_TSE_Msk

#define	RTC_CR_WUTE_Pos (10U)

#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

#define	RTC_CR_WUTE RTC_CR_WUTE_Msk

#define	RTC_CR_ALRBE_Pos (9U)

#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk

#define	RTC_CR_ALRAE_Pos (8U)

#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk

#define	RTC_CR_FMT_Pos (6U)

#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

#define	RTC_CR_FMT RTC_CR_FMT_Msk

#define	RTC_CR_BYPSHAD_Pos (5U)

#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

#define	RTC_CR_REFCKON_Pos (4U)

#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk

#define	RTC_CR_TSEDGE_Pos (3U)

#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

#define	RTC_CR_WUCKSEL_Pos (0U)

#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_BCK_Pos RTC_CR_BKP_Pos

#define	RTC_CR_BCK_Msk RTC_CR_BKP_Msk

#define	RTC_CR_BCK RTC_CR_BKP

#define	RTC_ISR_RECALPF_Pos (16U)

#define	RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)

#define	RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk

#define	RTC_ISR_TAMP2F_Pos (14U)

#define	RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)

#define	RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk

#define	RTC_ISR_TAMP1F_Pos (13U)

#define	RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)

#define	RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk

#define	RTC_ISR_TSOVF_Pos (12U)

#define	RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)

#define	RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk

#define	RTC_ISR_TSF_Pos (11U)

#define	RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)

#define	RTC_ISR_TSF RTC_ISR_TSF_Msk

#define	RTC_ISR_WUTF_Pos (10U)

#define	RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)

#define	RTC_ISR_WUTF RTC_ISR_WUTF_Msk

#define	RTC_ISR_ALRBF_Pos (9U)

#define	RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)

#define	RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk

#define	RTC_ISR_ALRAF_Pos (8U)

#define	RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)

#define	RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk

#define	RTC_ISR_INIT_Pos (7U)

#define	RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)

#define	RTC_ISR_INIT RTC_ISR_INIT_Msk

#define	RTC_ISR_INITF_Pos (6U)

#define	RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)

#define	RTC_ISR_INITF RTC_ISR_INITF_Msk

#define	RTC_ISR_RSF_Pos (5U)

#define	RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)

#define	RTC_ISR_RSF RTC_ISR_RSF_Msk

#define	RTC_ISR_INITS_Pos (4U)

#define	RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)

#define	RTC_ISR_INITS RTC_ISR_INITS_Msk

#define	RTC_ISR_SHPF_Pos (3U)

#define	RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)

#define	RTC_ISR_SHPF RTC_ISR_SHPF_Msk

#define	RTC_ISR_WUTWF_Pos (2U)

#define	RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)

#define	RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk

#define	RTC_ISR_ALRBWF_Pos (1U)

#define	RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)

#define	RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk

#define	RTC_ISR_ALRAWF_Pos (0U)

#define	RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)

#define	RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk

#define	RTC_PRER_PREDIV_A_Pos (16U)

#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

#define	RTC_PRER_PREDIV_S_Pos (0U)

#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

#define	RTC_WUTR_WUT_Pos (0U)

#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk

#define	RTC_ALRMAR_MSK4_Pos (31U)

#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

#define	RTC_ALRMAR_WDSEL_Pos (30U)

#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

#define	RTC_ALRMAR_DT_Pos (28U)

#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DU_Pos (24U)

#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_MSK3_Pos (23U)

#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

#define	RTC_ALRMAR_PM_Pos (22U)

#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

#define	RTC_ALRMAR_HT_Pos (20U)

#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HU_Pos (16U)

#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_MSK2_Pos (15U)

#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

#define	RTC_ALRMAR_MNT_Pos (12U)

#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNU_Pos (8U)

#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MSK1_Pos (7U)

#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

#define	RTC_ALRMAR_ST_Pos (4U)

#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_SU_Pos (0U)

#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMBR_MSK4_Pos (31U)

#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

#define	RTC_ALRMBR_WDSEL_Pos (30U)

#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

#define	RTC_ALRMBR_DT_Pos (28U)

#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DU_Pos (24U)

#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_MSK3_Pos (23U)

#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

#define	RTC_ALRMBR_PM_Pos (22U)

#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

#define	RTC_ALRMBR_HT_Pos (20U)

#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HU_Pos (16U)

#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_MSK2_Pos (15U)

#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

#define	RTC_ALRMBR_MNT_Pos (12U)

#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNU_Pos (8U)

#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MSK1_Pos (7U)

#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

#define	RTC_ALRMBR_ST_Pos (4U)

#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_SU_Pos (0U)

#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

#define	RTC_WPR_KEY_Pos (0U)

#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

#define	RTC_WPR_KEY RTC_WPR_KEY_Msk

#define	RTC_SSR_SS_Pos (0U)

#define	RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

#define	RTC_SSR_SS RTC_SSR_SS_Msk

#define	RTC_SHIFTR_SUBFS_Pos (0U)

#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

#define	RTC_SHIFTR_ADD1S_Pos (31U)

#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

#define	RTC_TSTR_PM_Pos (22U)

#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

#define	RTC_TSTR_PM RTC_TSTR_PM_Msk

#define	RTC_TSTR_HT_Pos (20U)

#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT RTC_TSTR_HT_Msk

#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HU_Pos (16U)

#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU RTC_TSTR_HU_Msk

#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_MNT_Pos (12U)

#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk

#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNU_Pos (8U)

#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk

#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_ST_Pos (4U)

#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST RTC_TSTR_ST_Msk

#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_SU_Pos (0U)

#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU RTC_TSTR_SU_Msk

#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

#define	RTC_TSDR_WDU_Pos (13U)

#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk

#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_MT_Pos (12U)

#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

#define	RTC_TSDR_MT RTC_TSDR_MT_Msk

#define	RTC_TSDR_MU_Pos (8U)

#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU RTC_TSDR_MU_Msk

#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_DT_Pos (4U)

#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT RTC_TSDR_DT_Msk

#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DU_Pos (0U)

#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU RTC_TSDR_DU_Msk

#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

#define	RTC_TSSSR_SS_Pos (0U)

#define	RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk

#define	RTC_CALR_CALP_Pos (15U)

#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

#define	RTC_CALR_CALP RTC_CALR_CALP_Msk

#define	RTC_CALR_CALW8_Pos (14U)

#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

#define	RTC_CALR_CALW16_Pos (13U)

#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

#define	RTC_CALR_CALM_Pos (0U)

#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM RTC_CALR_CALM_Msk

#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

#define	RTC_TAFCR_PC15MODE_Pos (23U)

#define	RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos)

#define	RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk

#define	RTC_TAFCR_PC15VALUE_Pos (22U)

#define	RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos)

#define	RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk

#define	RTC_TAFCR_PC14MODE_Pos (21U)

#define	RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos)

#define	RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk

#define	RTC_TAFCR_PC14VALUE_Pos (20U)

#define	RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos)

#define	RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk

#define	RTC_TAFCR_PC13MODE_Pos (19U)

#define	RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos)

#define	RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk

#define	RTC_TAFCR_PC13VALUE_Pos (18U)

#define	RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos)

#define	RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk

#define	RTC_TAFCR_TAMPPUDIS_Pos (15U)

#define	RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)

#define	RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk

#define	RTC_TAFCR_TAMPPRCH_Pos (13U)

#define	RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk

#define	RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPFLT_Pos (11U)

#define	RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk

#define	RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFREQ_Pos (8U)

#define	RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk

#define	RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPTS_Pos (7U)

#define	RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)

#define	RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk

#define	RTC_TAFCR_TAMP2TRG_Pos (4U)

#define	RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)

#define	RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk

#define	RTC_TAFCR_TAMP2E_Pos (3U)

#define	RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)

#define	RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk

#define	RTC_TAFCR_TAMPIE_Pos (2U)

#define	RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)

#define	RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk

#define	RTC_TAFCR_TAMP1TRG_Pos (1U)

#define	RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)

#define	RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk

#define	RTC_TAFCR_TAMP1E_Pos (0U)

#define	RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)

#define	RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk

#define	RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE

#define	RTC_ALRMASSR_MASKSS_Pos (24U)

#define	RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_SS_Pos (0U)

#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

#define	RTC_ALRMBSSR_MASKSS_Pos (24U)

#define	RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_SS_Pos (0U)

#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

#define	RTC_BKP0R_Pos (0U)

#define	RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)

#define	RTC_BKP0R RTC_BKP0R_Msk

#define	RTC_BKP1R_Pos (0U)

#define	RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)

#define	RTC_BKP1R RTC_BKP1R_Msk

#define	RTC_BKP2R_Pos (0U)

#define	RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)

#define	RTC_BKP2R RTC_BKP2R_Msk

#define	RTC_BKP3R_Pos (0U)

#define	RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)

#define	RTC_BKP3R RTC_BKP3R_Msk

#define	RTC_BKP4R_Pos (0U)

#define	RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)

#define	RTC_BKP4R RTC_BKP4R_Msk

#define	RTC_BKP_NUMBER 5

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_CRCL_Pos (11U)

#define	SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

#define	SPI_CR1_CRCL SPI_CR1_CRCL_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_NSSP_Pos (3U)

#define	SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

#define	SPI_CR2_NSSP SPI_CR2_NSSP_Msk

#define	SPI_CR2_FRF_Pos (4U)

#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

#define	SPI_CR2_FRF SPI_CR2_FRF_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_CR2_DS_Pos (8U)

#define	SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS SPI_CR2_DS_Msk

#define	SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_FRXTH_Pos (12U)

#define	SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

#define	SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

#define	SPI_CR2_LDMARX_Pos (13U)

#define	SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

#define	SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

#define	SPI_CR2_LDMATX_Pos (14U)

#define	SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

#define	SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_SR_FRE_Pos (8U)

#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

#define	SPI_SR_FRE SPI_SR_FRE_Msk

#define	SPI_SR_FRLVL_Pos (9U)

#define	SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL SPI_SR_FRLVL_Msk

#define	SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FTLVL_Pos (11U)

#define	SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL SPI_SR_FTLVL_Msk

#define	SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SYSCFG_CFGR1_MEM_MODE_Pos (0U)

#define	SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk

#define	SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U)

#define	SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U)

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos)

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos)

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk

#define	SYSCFG_CFGR1_DMA_RMP_Pos (11U)

#define	SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)

#define	SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)

#define	SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk

#define	SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos (15U)

#define	SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_DAC2Ch1_DMA_RMP SYSCFG_CFGR1_DAC2Ch1_DMA_RMP_Msk

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define	SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

#define	SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

#define	SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)

#define	SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk

#define	SYSCFG_CFGR1_FPU_IE_Pos (26U)

#define	SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk

#define	SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_RCR_PAGE0_Pos (0U)

#define	SYSCFG_RCR_PAGE0_Msk (0x1UL << SYSCFG_RCR_PAGE0_Pos)

#define	SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk

#define	SYSCFG_RCR_PAGE1_Pos (1U)

#define	SYSCFG_RCR_PAGE1_Msk (0x1UL << SYSCFG_RCR_PAGE1_Pos)

#define	SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk

#define	SYSCFG_RCR_PAGE2_Pos (2U)

#define	SYSCFG_RCR_PAGE2_Msk (0x1UL << SYSCFG_RCR_PAGE2_Pos)

#define	SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk

#define	SYSCFG_RCR_PAGE3_Pos (3U)

#define	SYSCFG_RCR_PAGE3_Msk (0x1UL << SYSCFG_RCR_PAGE3_Pos)

#define	SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk

#define	SYSCFG_EXTICR1_EXTI0_Pos (0U)

#define	SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)

#define	SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

#define	SYSCFG_EXTICR1_EXTI1_Pos (4U)

#define	SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)

#define	SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

#define	SYSCFG_EXTICR1_EXTI2_Pos (8U)

#define	SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)

#define	SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

#define	SYSCFG_EXTICR1_EXTI3_Pos (12U)

#define	SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)

#define	SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
	EXTI0 configuration. More...

#define	SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

#define	SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

#define	SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)

#define	SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)

#define	SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
	EXTI1 configuration. More...

#define	SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

#define	SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

#define	SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)

#define	SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)

#define	SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
	EXTI2 configuration. More...

#define	SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

#define	SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

#define	SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)

#define	SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)

#define	SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
	EXTI3 configuration. More...

#define	SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

#define	SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

#define	SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)

#define	SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)

#define	SYSCFG_EXTICR2_EXTI4_Pos (0U)

#define	SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)

#define	SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

#define	SYSCFG_EXTICR2_EXTI5_Pos (4U)

#define	SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)

#define	SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

#define	SYSCFG_EXTICR2_EXTI6_Pos (8U)

#define	SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)

#define	SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

#define	SYSCFG_EXTICR2_EXTI7_Pos (12U)

#define	SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)

#define	SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
	EXTI4 configuration. More...

#define	SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

#define	SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

#define	SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)

#define	SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)

#define	SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
	EXTI5 configuration. More...

#define	SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

#define	SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

#define	SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)

#define	SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)

#define	SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
	EXTI6 configuration. More...

#define	SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

#define	SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

#define	SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)

#define	SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)

#define	SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
	EXTI7 configuration. More...

#define	SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

#define	SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)

#define	SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)

#define	SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)

#define	SYSCFG_EXTICR3_EXTI8_Pos (0U)

#define	SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)

#define	SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

#define	SYSCFG_EXTICR3_EXTI9_Pos (4U)

#define	SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)

#define	SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

#define	SYSCFG_EXTICR3_EXTI10_Pos (8U)

#define	SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)

#define	SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

#define	SYSCFG_EXTICR3_EXTI11_Pos (12U)

#define	SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)

#define	SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
	EXTI8 configuration. More...

#define	SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

#define	SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)

#define	SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)

#define	SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
	EXTI9 configuration. More...

#define	SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

#define	SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)

#define	SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)

#define	SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)

#define	SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
	EXTI10 configuration. More...

#define	SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

#define	SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)

#define	SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)

#define	SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)

#define	SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
	EXTI11 configuration. More...

#define	SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

#define	SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)

#define	SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)

#define	SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)

#define	SYSCFG_EXTICR4_EXTI12_Pos (0U)

#define	SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)

#define	SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

#define	SYSCFG_EXTICR4_EXTI13_Pos (4U)

#define	SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)

#define	SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

#define	SYSCFG_EXTICR4_EXTI14_Pos (8U)

#define	SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)

#define	SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

#define	SYSCFG_EXTICR4_EXTI15_Pos (12U)

#define	SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)

#define	SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
	EXTI12 configuration. More...

#define	SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

#define	SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)

#define	SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)

#define	SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
	EXTI13 configuration. More...

#define	SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

#define	SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

#define	SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)

#define	SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
	EXTI14 configuration. More...

#define	SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

#define	SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

#define	SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)

#define	SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
	EXTI15 configuration. More...

#define	SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

#define	SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

#define	SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)

#define	SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)

#define	SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)

#define	SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)

#define	SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos)

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk

#define	SYSCFG_CFGR2_PVD_LOCK_Pos (2U)

#define	SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)

#define	SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk

#define	SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)

#define	SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos)

#define	SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk

#define	SYSCFG_CFGR2_SRAM_PE_Pos (8U)

#define	SYSCFG_CFGR2_SRAM_PE_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos)

#define	SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk

#define	SYSCFG_CFGR3_DMA_RMP_Pos (0U)

#define	SYSCFG_CFGR3_DMA_RMP_Msk (0x3FFUL << SYSCFG_CFGR3_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_DMA_RMP SYSCFG_CFGR3_DMA_RMP_Msk

#define	SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos (0U)

#define	SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_SPI1_RX_DMA_RMP SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Msk

#define	SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_SPI1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos (2U)

#define	SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_SPI1_TX_DMA_RMP SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Msk

#define	SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_SPI1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos (4U)

#define	SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_RX_DMA_RMP SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Msk

#define	SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_I2C1_RX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos (6U)

#define	SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_TX_DMA_RMP SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Msk

#define	SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_I2C1_TX_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_ADC2_DMA_RMP_Pos (8U)

#define	SYSCFG_CFGR3_ADC2_DMA_RMP_Msk (0x3UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_ADC2_DMA_RMP SYSCFG_CFGR3_ADC2_DMA_RMP_Msk

#define	SYSCFG_CFGR3_ADC2_DMA_RMP_0 (0x1UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_ADC2_DMA_RMP_1 (0x2UL << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos)

#define	SYSCFG_CFGR3_TRIGGER_RMP_Pos (16U)

#define	SYSCFG_CFGR3_TRIGGER_RMP_Msk (0x3UL << SYSCFG_CFGR3_TRIGGER_RMP_Pos)

#define	SYSCFG_CFGR3_TRIGGER_RMP SYSCFG_CFGR3_TRIGGER_RMP_Msk

#define	SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos (16U)

#define	SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk (0x1UL << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos)

#define	SYSCFG_CFGR3_DAC1_TRG3_RMP SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk

#define	SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos (17U)

#define	SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk (0x1UL << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos)

#define	SYSCFG_CFGR3_DAC1_TRG5_RMP SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_UIFREMAP_Pos (11U)

#define	TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

#define	TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_CR2_OIS5_Pos (16U)

#define	TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

#define	TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

#define	TIM_CR2_OIS6_Pos (18U)

#define	TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

#define	TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

#define	TIM_CR2_MMS2_Pos (20U)

#define	TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

#define	TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x00000001U)

#define	TIM_SMCR_SMS_1 (0x00000002U)

#define	TIM_SMCR_SMS_2 (0x00000004U)

#define	TIM_SMCR_SMS_3 (0x00010000U)

#define	TIM_SMCR_OCCS_Pos (3U)

#define	TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

#define	TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_B2IF_Pos (8U)

#define	TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

#define	TIM_SR_B2IF TIM_SR_B2IF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_SR_CC5IF_Pos (16U)

#define	TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

#define	TIM_SR_CC5IF TIM_SR_CC5IF_Msk

#define	TIM_SR_CC6IF_Pos (17U)

#define	TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

#define	TIM_SR_CC6IF TIM_SR_CC6IF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_EGR_B2G_Pos (8U)

#define	TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

#define	TIM_EGR_B2G TIM_EGR_B2G_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x00000010U)

#define	TIM_CCMR1_OC1M_1 (0x00000020U)

#define	TIM_CCMR1_OC1M_2 (0x00000040U)

#define	TIM_CCMR1_OC1M_3 (0x00010000U)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x00001000U)

#define	TIM_CCMR1_OC2M_1 (0x00002000U)

#define	TIM_CCMR1_OC2M_2 (0x00004000U)

#define	TIM_CCMR1_OC2M_3 (0x01000000U)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x00000010U)

#define	TIM_CCMR2_OC3M_1 (0x00000020U)

#define	TIM_CCMR2_OC3M_2 (0x00000040U)

#define	TIM_CCMR2_OC3M_3 (0x00010000U)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x00001000U)

#define	TIM_CCMR2_OC4M_1 (0x00002000U)

#define	TIM_CCMR2_OC4M_2 (0x00004000U)

#define	TIM_CCMR2_OC4M_3 (0x01000000U)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CCER_CC4NP_Pos (15U)

#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

#define	TIM_CCER_CC5E_Pos (16U)

#define	TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

#define	TIM_CCER_CC5E TIM_CCER_CC5E_Msk

#define	TIM_CCER_CC5P_Pos (17U)

#define	TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

#define	TIM_CCER_CC5P TIM_CCER_CC5P_Msk

#define	TIM_CCER_CC6E_Pos (20U)

#define	TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

#define	TIM_CCER_CC6E TIM_CCER_CC6E_Msk

#define	TIM_CCER_CC6P_Pos (21U)

#define	TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

#define	TIM_CCER_CC6P TIM_CCER_CC6P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_CNT_UIFCPY_Pos (31U)

#define	TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

#define	TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_CCR5_CCR5_Pos (0U)

#define	TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

#define	TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

#define	TIM_CCR5_GC5C1_Pos (29U)

#define	TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

#define	TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

#define	TIM_CCR5_GC5C2_Pos (30U)

#define	TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

#define	TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

#define	TIM_CCR5_GC5C3_Pos (31U)

#define	TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

#define	TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

#define	TIM_CCR6_CCR6_Pos (0U)

#define	TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

#define	TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_BDTR_BKF_Pos (16U)

#define	TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

#define	TIM_BDTR_BKF TIM_BDTR_BKF_Msk

#define	TIM_BDTR_BK2F_Pos (20U)

#define	TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

#define	TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

#define	TIM_BDTR_BK2E_Pos (24U)

#define	TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

#define	TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

#define	TIM_BDTR_BK2P_Pos (25U)

#define	TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

#define	TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	TIM16_OR_TI1_RMP_Pos (0U)

#define	TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk

#define	TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM1_OR_ETR_RMP_Pos (0U)

#define	TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk

#define	TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM_CCMR3_OC5FE_Pos (2U)

#define	TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

#define	TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

#define	TIM_CCMR3_OC5PE_Pos (3U)

#define	TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

#define	TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

#define	TIM_CCMR3_OC5M_Pos (4U)

#define	TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

#define	TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5CE_Pos (7U)

#define	TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

#define	TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

#define	TIM_CCMR3_OC6FE_Pos (10U)

#define	TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

#define	TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

#define	TIM_CCMR3_OC6PE_Pos (11U)

#define	TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

#define	TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

#define	TIM_CCMR3_OC6M_Pos (12U)

#define	TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

#define	TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6CE_Pos (15U)

#define	TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

#define	TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

#define	TSC_CR_TSCE_Pos (0U)

#define	TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)

#define	TSC_CR_TSCE TSC_CR_TSCE_Msk

#define	TSC_CR_START_Pos (1U)

#define	TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)

#define	TSC_CR_START TSC_CR_START_Msk

#define	TSC_CR_AM_Pos (2U)

#define	TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)

#define	TSC_CR_AM TSC_CR_AM_Msk

#define	TSC_CR_SYNCPOL_Pos (3U)

#define	TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)

#define	TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk

#define	TSC_CR_IODEF_Pos (4U)

#define	TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)

#define	TSC_CR_IODEF TSC_CR_IODEF_Msk

#define	TSC_CR_MCV_Pos (5U)

#define	TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV TSC_CR_MCV_Msk

#define	TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)

#define	TSC_CR_PGPSC_Pos (12U)

#define	TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC TSC_CR_PGPSC_Msk

#define	TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_SSPSC_Pos (15U)

#define	TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)

#define	TSC_CR_SSPSC TSC_CR_SSPSC_Msk

#define	TSC_CR_SSE_Pos (16U)

#define	TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)

#define	TSC_CR_SSE TSC_CR_SSE_Msk

#define	TSC_CR_SSD_Pos (17U)

#define	TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD TSC_CR_SSD_Msk

#define	TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)

#define	TSC_CR_CTPL_Pos (24U)

#define	TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL TSC_CR_CTPL_Msk

#define	TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPH_Pos (28U)

#define	TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH TSC_CR_CTPH_Msk

#define	TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)

#define	TSC_IER_EOAIE_Pos (0U)

#define	TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)

#define	TSC_IER_EOAIE TSC_IER_EOAIE_Msk

#define	TSC_IER_MCEIE_Pos (1U)

#define	TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)

#define	TSC_IER_MCEIE TSC_IER_MCEIE_Msk

#define	TSC_ICR_EOAIC_Pos (0U)

#define	TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)

#define	TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk

#define	TSC_ICR_MCEIC_Pos (1U)

#define	TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)

#define	TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk

#define	TSC_ISR_EOAF_Pos (0U)

#define	TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)

#define	TSC_ISR_EOAF TSC_ISR_EOAF_Msk

#define	TSC_ISR_MCEF_Pos (1U)

#define	TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)

#define	TSC_ISR_MCEF TSC_ISR_MCEF_Msk

#define	TSC_IOHCR_G1_IO1_Pos (0U)

#define	TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)

#define	TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk

#define	TSC_IOHCR_G1_IO2_Pos (1U)

#define	TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)

#define	TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk

#define	TSC_IOHCR_G1_IO3_Pos (2U)

#define	TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)

#define	TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk

#define	TSC_IOHCR_G1_IO4_Pos (3U)

#define	TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)

#define	TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk

#define	TSC_IOHCR_G2_IO1_Pos (4U)

#define	TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)

#define	TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk

#define	TSC_IOHCR_G2_IO2_Pos (5U)

#define	TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)

#define	TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk

#define	TSC_IOHCR_G2_IO3_Pos (6U)

#define	TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)

#define	TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk

#define	TSC_IOHCR_G2_IO4_Pos (7U)

#define	TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)

#define	TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk

#define	TSC_IOHCR_G3_IO1_Pos (8U)

#define	TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)

#define	TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk

#define	TSC_IOHCR_G3_IO2_Pos (9U)

#define	TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)

#define	TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk

#define	TSC_IOHCR_G3_IO3_Pos (10U)

#define	TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)

#define	TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk

#define	TSC_IOHCR_G3_IO4_Pos (11U)

#define	TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)

#define	TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk

#define	TSC_IOHCR_G4_IO1_Pos (12U)

#define	TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)

#define	TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk

#define	TSC_IOHCR_G4_IO2_Pos (13U)

#define	TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)

#define	TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk

#define	TSC_IOHCR_G4_IO3_Pos (14U)

#define	TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)

#define	TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk

#define	TSC_IOHCR_G4_IO4_Pos (15U)

#define	TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)

#define	TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk

#define	TSC_IOHCR_G5_IO1_Pos (16U)

#define	TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)

#define	TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk

#define	TSC_IOHCR_G5_IO2_Pos (17U)

#define	TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)

#define	TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk

#define	TSC_IOHCR_G5_IO3_Pos (18U)

#define	TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)

#define	TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk

#define	TSC_IOHCR_G5_IO4_Pos (19U)

#define	TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)

#define	TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk

#define	TSC_IOHCR_G6_IO1_Pos (20U)

#define	TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)

#define	TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk

#define	TSC_IOHCR_G6_IO2_Pos (21U)

#define	TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)

#define	TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk

#define	TSC_IOHCR_G6_IO3_Pos (22U)

#define	TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)

#define	TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk

#define	TSC_IOHCR_G6_IO4_Pos (23U)

#define	TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)

#define	TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk

#define	TSC_IOHCR_G7_IO1_Pos (24U)

#define	TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)

#define	TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk

#define	TSC_IOHCR_G7_IO2_Pos (25U)

#define	TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)

#define	TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk

#define	TSC_IOHCR_G7_IO3_Pos (26U)

#define	TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)

#define	TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk

#define	TSC_IOHCR_G7_IO4_Pos (27U)

#define	TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)

#define	TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk

#define	TSC_IOHCR_G8_IO1_Pos (28U)

#define	TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)

#define	TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk

#define	TSC_IOHCR_G8_IO2_Pos (29U)

#define	TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)

#define	TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk

#define	TSC_IOHCR_G8_IO3_Pos (30U)

#define	TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)

#define	TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk

#define	TSC_IOHCR_G8_IO4_Pos (31U)

#define	TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)

#define	TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk

#define	TSC_IOASCR_G1_IO1_Pos (0U)

#define	TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)

#define	TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk

#define	TSC_IOASCR_G1_IO2_Pos (1U)

#define	TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)

#define	TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk

#define	TSC_IOASCR_G1_IO3_Pos (2U)

#define	TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)

#define	TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk

#define	TSC_IOASCR_G1_IO4_Pos (3U)

#define	TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)

#define	TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk

#define	TSC_IOASCR_G2_IO1_Pos (4U)

#define	TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)

#define	TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk

#define	TSC_IOASCR_G2_IO2_Pos (5U)

#define	TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)

#define	TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk

#define	TSC_IOASCR_G2_IO3_Pos (6U)

#define	TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)

#define	TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk

#define	TSC_IOASCR_G2_IO4_Pos (7U)

#define	TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)

#define	TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk

#define	TSC_IOASCR_G3_IO1_Pos (8U)

#define	TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)

#define	TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk

#define	TSC_IOASCR_G3_IO2_Pos (9U)

#define	TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)

#define	TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk

#define	TSC_IOASCR_G3_IO3_Pos (10U)

#define	TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)

#define	TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk

#define	TSC_IOASCR_G3_IO4_Pos (11U)

#define	TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)

#define	TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk

#define	TSC_IOASCR_G4_IO1_Pos (12U)

#define	TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)

#define	TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk

#define	TSC_IOASCR_G4_IO2_Pos (13U)

#define	TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)

#define	TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk

#define	TSC_IOASCR_G4_IO3_Pos (14U)

#define	TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)

#define	TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk

#define	TSC_IOASCR_G4_IO4_Pos (15U)

#define	TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)

#define	TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk

#define	TSC_IOASCR_G5_IO1_Pos (16U)

#define	TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)

#define	TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk

#define	TSC_IOASCR_G5_IO2_Pos (17U)

#define	TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)

#define	TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk

#define	TSC_IOASCR_G5_IO3_Pos (18U)

#define	TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)

#define	TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk

#define	TSC_IOASCR_G5_IO4_Pos (19U)

#define	TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)

#define	TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk

#define	TSC_IOASCR_G6_IO1_Pos (20U)

#define	TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)

#define	TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk

#define	TSC_IOASCR_G6_IO2_Pos (21U)

#define	TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)

#define	TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk

#define	TSC_IOASCR_G6_IO3_Pos (22U)

#define	TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)

#define	TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk

#define	TSC_IOASCR_G6_IO4_Pos (23U)

#define	TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)

#define	TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk

#define	TSC_IOASCR_G7_IO1_Pos (24U)

#define	TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)

#define	TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk

#define	TSC_IOASCR_G7_IO2_Pos (25U)

#define	TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)

#define	TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk

#define	TSC_IOASCR_G7_IO3_Pos (26U)

#define	TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)

#define	TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk

#define	TSC_IOASCR_G7_IO4_Pos (27U)

#define	TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)

#define	TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk

#define	TSC_IOASCR_G8_IO1_Pos (28U)

#define	TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)

#define	TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk

#define	TSC_IOASCR_G8_IO2_Pos (29U)

#define	TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)

#define	TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk

#define	TSC_IOASCR_G8_IO3_Pos (30U)

#define	TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)

#define	TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk

#define	TSC_IOASCR_G8_IO4_Pos (31U)

#define	TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)

#define	TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk

#define	TSC_IOSCR_G1_IO1_Pos (0U)

#define	TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)

#define	TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk

#define	TSC_IOSCR_G1_IO2_Pos (1U)

#define	TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)

#define	TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk

#define	TSC_IOSCR_G1_IO3_Pos (2U)

#define	TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)

#define	TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk

#define	TSC_IOSCR_G1_IO4_Pos (3U)

#define	TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)

#define	TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk

#define	TSC_IOSCR_G2_IO1_Pos (4U)

#define	TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)

#define	TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk

#define	TSC_IOSCR_G2_IO2_Pos (5U)

#define	TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)

#define	TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk

#define	TSC_IOSCR_G2_IO3_Pos (6U)

#define	TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)

#define	TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk

#define	TSC_IOSCR_G2_IO4_Pos (7U)

#define	TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)

#define	TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk

#define	TSC_IOSCR_G3_IO1_Pos (8U)

#define	TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)

#define	TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk

#define	TSC_IOSCR_G3_IO2_Pos (9U)

#define	TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)

#define	TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk

#define	TSC_IOSCR_G3_IO3_Pos (10U)

#define	TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)

#define	TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk

#define	TSC_IOSCR_G3_IO4_Pos (11U)

#define	TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)

#define	TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk

#define	TSC_IOSCR_G4_IO1_Pos (12U)

#define	TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)

#define	TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk

#define	TSC_IOSCR_G4_IO2_Pos (13U)

#define	TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)

#define	TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk

#define	TSC_IOSCR_G4_IO3_Pos (14U)

#define	TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)

#define	TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk

#define	TSC_IOSCR_G4_IO4_Pos (15U)

#define	TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)

#define	TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk

#define	TSC_IOSCR_G5_IO1_Pos (16U)

#define	TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)

#define	TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk

#define	TSC_IOSCR_G5_IO2_Pos (17U)

#define	TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)

#define	TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk

#define	TSC_IOSCR_G5_IO3_Pos (18U)

#define	TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)

#define	TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk

#define	TSC_IOSCR_G5_IO4_Pos (19U)

#define	TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)

#define	TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk

#define	TSC_IOSCR_G6_IO1_Pos (20U)

#define	TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)

#define	TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk

#define	TSC_IOSCR_G6_IO2_Pos (21U)

#define	TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)

#define	TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk

#define	TSC_IOSCR_G6_IO3_Pos (22U)

#define	TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)

#define	TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk

#define	TSC_IOSCR_G6_IO4_Pos (23U)

#define	TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)

#define	TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk

#define	TSC_IOSCR_G7_IO1_Pos (24U)

#define	TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)

#define	TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk

#define	TSC_IOSCR_G7_IO2_Pos (25U)

#define	TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)

#define	TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk

#define	TSC_IOSCR_G7_IO3_Pos (26U)

#define	TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)

#define	TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk

#define	TSC_IOSCR_G7_IO4_Pos (27U)

#define	TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)

#define	TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk

#define	TSC_IOSCR_G8_IO1_Pos (28U)

#define	TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)

#define	TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk

#define	TSC_IOSCR_G8_IO2_Pos (29U)

#define	TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)

#define	TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk

#define	TSC_IOSCR_G8_IO3_Pos (30U)

#define	TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)

#define	TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk

#define	TSC_IOSCR_G8_IO4_Pos (31U)

#define	TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)

#define	TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk

#define	TSC_IOCCR_G1_IO1_Pos (0U)

#define	TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)

#define	TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk

#define	TSC_IOCCR_G1_IO2_Pos (1U)

#define	TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)

#define	TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk

#define	TSC_IOCCR_G1_IO3_Pos (2U)

#define	TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)

#define	TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk

#define	TSC_IOCCR_G1_IO4_Pos (3U)

#define	TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)

#define	TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk

#define	TSC_IOCCR_G2_IO1_Pos (4U)

#define	TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)

#define	TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk

#define	TSC_IOCCR_G2_IO2_Pos (5U)

#define	TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)

#define	TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk

#define	TSC_IOCCR_G2_IO3_Pos (6U)

#define	TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)

#define	TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk

#define	TSC_IOCCR_G2_IO4_Pos (7U)

#define	TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)

#define	TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk

#define	TSC_IOCCR_G3_IO1_Pos (8U)

#define	TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)

#define	TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk

#define	TSC_IOCCR_G3_IO2_Pos (9U)

#define	TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)

#define	TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk

#define	TSC_IOCCR_G3_IO3_Pos (10U)

#define	TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)

#define	TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk

#define	TSC_IOCCR_G3_IO4_Pos (11U)

#define	TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)

#define	TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk

#define	TSC_IOCCR_G4_IO1_Pos (12U)

#define	TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)

#define	TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk

#define	TSC_IOCCR_G4_IO2_Pos (13U)

#define	TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)

#define	TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk

#define	TSC_IOCCR_G4_IO3_Pos (14U)

#define	TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)

#define	TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk

#define	TSC_IOCCR_G4_IO4_Pos (15U)

#define	TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)

#define	TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk

#define	TSC_IOCCR_G5_IO1_Pos (16U)

#define	TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)

#define	TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk

#define	TSC_IOCCR_G5_IO2_Pos (17U)

#define	TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)

#define	TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk

#define	TSC_IOCCR_G5_IO3_Pos (18U)

#define	TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)

#define	TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk

#define	TSC_IOCCR_G5_IO4_Pos (19U)

#define	TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)

#define	TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk

#define	TSC_IOCCR_G6_IO1_Pos (20U)

#define	TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)

#define	TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk

#define	TSC_IOCCR_G6_IO2_Pos (21U)

#define	TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)

#define	TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk

#define	TSC_IOCCR_G6_IO3_Pos (22U)

#define	TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)

#define	TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk

#define	TSC_IOCCR_G6_IO4_Pos (23U)

#define	TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)

#define	TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk

#define	TSC_IOCCR_G7_IO1_Pos (24U)

#define	TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)

#define	TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk

#define	TSC_IOCCR_G7_IO2_Pos (25U)

#define	TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)

#define	TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk

#define	TSC_IOCCR_G7_IO3_Pos (26U)

#define	TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)

#define	TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk

#define	TSC_IOCCR_G7_IO4_Pos (27U)

#define	TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)

#define	TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk

#define	TSC_IOCCR_G8_IO1_Pos (28U)

#define	TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)

#define	TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk

#define	TSC_IOCCR_G8_IO2_Pos (29U)

#define	TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)

#define	TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk

#define	TSC_IOCCR_G8_IO3_Pos (30U)

#define	TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)

#define	TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk

#define	TSC_IOCCR_G8_IO4_Pos (31U)

#define	TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)

#define	TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk

#define	TSC_IOGCSR_G1E_Pos (0U)

#define	TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)

#define	TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk

#define	TSC_IOGCSR_G2E_Pos (1U)

#define	TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)

#define	TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk

#define	TSC_IOGCSR_G3E_Pos (2U)

#define	TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)

#define	TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk

#define	TSC_IOGCSR_G4E_Pos (3U)

#define	TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)

#define	TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk

#define	TSC_IOGCSR_G5E_Pos (4U)

#define	TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)

#define	TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk

#define	TSC_IOGCSR_G6E_Pos (5U)

#define	TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)

#define	TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk

#define	TSC_IOGCSR_G7E_Pos (6U)

#define	TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)

#define	TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk

#define	TSC_IOGCSR_G8E_Pos (7U)

#define	TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)

#define	TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk

#define	TSC_IOGCSR_G1S_Pos (16U)

#define	TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)

#define	TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk

#define	TSC_IOGCSR_G2S_Pos (17U)

#define	TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)

#define	TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk

#define	TSC_IOGCSR_G3S_Pos (18U)

#define	TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)

#define	TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk

#define	TSC_IOGCSR_G4S_Pos (19U)

#define	TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)

#define	TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk

#define	TSC_IOGCSR_G5S_Pos (20U)

#define	TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)

#define	TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk

#define	TSC_IOGCSR_G6S_Pos (21U)

#define	TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)

#define	TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk

#define	TSC_IOGCSR_G7S_Pos (22U)

#define	TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)

#define	TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk

#define	TSC_IOGCSR_G8S_Pos (23U)

#define	TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)

#define	TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk

#define	TSC_IOGXCR_CNT_Pos (0U)

#define	TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)

#define	TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk

#define	USART_7BITS_SUPPORT

#define	USART_CR1_UE_Pos (0U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR1_UESM_Pos (1U)

#define	USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

#define	USART_CR1_UESM USART_CR1_UESM_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

#define	USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_Pos (7U)

#define	USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

#define	USART_CR1_TXEIE USART_CR1_TXEIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M0_Pos (12U)

#define	USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

#define	USART_CR1_M0 USART_CR1_M0_Msk

#define	USART_CR1_MME_Pos (13U)

#define	USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

#define	USART_CR1_MME USART_CR1_MME_Msk

#define	USART_CR1_CMIE_Pos (14U)

#define	USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

#define	USART_CR1_CMIE USART_CR1_CMIE_Msk

#define	USART_CR1_OVER8_Pos (15U)

#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk

#define	USART_CR1_DEDT_Pos (16U)

#define	USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT USART_CR1_DEDT_Msk

#define	USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEAT_Pos (21U)

#define	USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT USART_CR1_DEAT_Msk

#define	USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_RTOIE_Pos (26U)

#define	USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

#define	USART_CR1_RTOIE USART_CR1_RTOIE_Msk

#define	USART_CR1_EOBIE_Pos (27U)

#define	USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

#define	USART_CR1_EOBIE USART_CR1_EOBIE_Msk

#define	USART_CR1_M1_Pos (28U)

#define	USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

#define	USART_CR1_M1 USART_CR1_M1_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR2_ADDM7_Pos (4U)

#define	USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

#define	USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR2_SWAP_Pos (15U)

#define	USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

#define	USART_CR2_SWAP USART_CR2_SWAP_Msk

#define	USART_CR2_RXINV_Pos (16U)

#define	USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

#define	USART_CR2_RXINV USART_CR2_RXINV_Msk

#define	USART_CR2_TXINV_Pos (17U)

#define	USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

#define	USART_CR2_TXINV USART_CR2_TXINV_Msk

#define	USART_CR2_DATAINV_Pos (18U)

#define	USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

#define	USART_CR2_DATAINV USART_CR2_DATAINV_Msk

#define	USART_CR2_MSBFIRST_Pos (19U)

#define	USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

#define	USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

#define	USART_CR2_ABREN_Pos (20U)

#define	USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

#define	USART_CR2_ABREN USART_CR2_ABREN_Msk

#define	USART_CR2_ABRMODE_Pos (21U)

#define	USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

#define	USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_RTOEN_Pos (23U)

#define	USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

#define	USART_CR2_RTOEN USART_CR2_RTOEN_Msk

#define	USART_CR2_ADD_Pos (24U)

#define	USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_CR3_ONEBIT_Pos (11U)

#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

#define	USART_CR3_OVRDIS_Pos (12U)

#define	USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

#define	USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

#define	USART_CR3_DDRE_Pos (13U)

#define	USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

#define	USART_CR3_DDRE USART_CR3_DDRE_Msk

#define	USART_CR3_DEM_Pos (14U)

#define	USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

#define	USART_CR3_DEM USART_CR3_DEM_Msk

#define	USART_CR3_DEP_Pos (15U)

#define	USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

#define	USART_CR3_DEP USART_CR3_DEP_Msk

#define	USART_CR3_SCARCNT_Pos (17U)

#define	USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

#define	USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_WUS_Pos (20U)

#define	USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS USART_CR3_WUS_Msk

#define	USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUFIE_Pos (22U)

#define	USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

#define	USART_CR3_WUFIE USART_CR3_WUFIE_Msk

#define	USART_BRR_DIV_FRACTION_Pos (0U)

#define	USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)

#define	USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk

#define	USART_BRR_DIV_MANTISSA_Pos (4U)

#define	USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)

#define	USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	USART_RTOR_RTO_Pos (0U)

#define	USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

#define	USART_RTOR_RTO USART_RTOR_RTO_Msk

#define	USART_RTOR_BLEN_Pos (24U)

#define	USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

#define	USART_RTOR_BLEN USART_RTOR_BLEN_Msk

#define	USART_RQR_ABRRQ_Pos (0U)

#define	USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)

#define	USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk

#define	USART_RQR_SBKRQ_Pos (1U)

#define	USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)

#define	USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk

#define	USART_RQR_MMRQ_Pos (2U)

#define	USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)

#define	USART_RQR_MMRQ USART_RQR_MMRQ_Msk

#define	USART_RQR_RXFRQ_Pos (3U)

#define	USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)

#define	USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk

#define	USART_RQR_TXFRQ_Pos (4U)

#define	USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)

#define	USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk

#define	USART_ISR_PE_Pos (0U)

#define	USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

#define	USART_ISR_PE USART_ISR_PE_Msk

#define	USART_ISR_FE_Pos (1U)

#define	USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

#define	USART_ISR_FE USART_ISR_FE_Msk

#define	USART_ISR_NE_Pos (2U)

#define	USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

#define	USART_ISR_NE USART_ISR_NE_Msk

#define	USART_ISR_ORE_Pos (3U)

#define	USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

#define	USART_ISR_ORE USART_ISR_ORE_Msk

#define	USART_ISR_IDLE_Pos (4U)

#define	USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

#define	USART_ISR_IDLE USART_ISR_IDLE_Msk

#define	USART_ISR_RXNE_Pos (5U)

#define	USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)

#define	USART_ISR_RXNE USART_ISR_RXNE_Msk

#define	USART_ISR_TC_Pos (6U)

#define	USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

#define	USART_ISR_TC USART_ISR_TC_Msk

#define	USART_ISR_TXE_Pos (7U)

#define	USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)

#define	USART_ISR_TXE USART_ISR_TXE_Msk

#define	USART_ISR_LBDF_Pos (8U)

#define	USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

#define	USART_ISR_LBDF USART_ISR_LBDF_Msk

#define	USART_ISR_CTSIF_Pos (9U)

#define	USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

#define	USART_ISR_CTSIF USART_ISR_CTSIF_Msk

#define	USART_ISR_CTS_Pos (10U)

#define	USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

#define	USART_ISR_CTS USART_ISR_CTS_Msk

#define	USART_ISR_RTOF_Pos (11U)

#define	USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

#define	USART_ISR_RTOF USART_ISR_RTOF_Msk

#define	USART_ISR_EOBF_Pos (12U)

#define	USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

#define	USART_ISR_EOBF USART_ISR_EOBF_Msk

#define	USART_ISR_ABRE_Pos (14U)

#define	USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

#define	USART_ISR_ABRE USART_ISR_ABRE_Msk

#define	USART_ISR_ABRF_Pos (15U)

#define	USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

#define	USART_ISR_ABRF USART_ISR_ABRF_Msk

#define	USART_ISR_BUSY_Pos (16U)

#define	USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

#define	USART_ISR_BUSY USART_ISR_BUSY_Msk

#define	USART_ISR_CMF_Pos (17U)

#define	USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

#define	USART_ISR_CMF USART_ISR_CMF_Msk

#define	USART_ISR_SBKF_Pos (18U)

#define	USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

#define	USART_ISR_SBKF USART_ISR_SBKF_Msk

#define	USART_ISR_RWU_Pos (19U)

#define	USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

#define	USART_ISR_RWU USART_ISR_RWU_Msk

#define	USART_ISR_WUF_Pos (20U)

#define	USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

#define	USART_ISR_WUF USART_ISR_WUF_Msk

#define	USART_ISR_TEACK_Pos (21U)

#define	USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

#define	USART_ISR_TEACK USART_ISR_TEACK_Msk

#define	USART_ISR_REACK_Pos (22U)

#define	USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

#define	USART_ISR_REACK USART_ISR_REACK_Msk

#define	USART_ICR_PECF_Pos (0U)

#define	USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

#define	USART_ICR_PECF USART_ICR_PECF_Msk

#define	USART_ICR_FECF_Pos (1U)

#define	USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

#define	USART_ICR_FECF USART_ICR_FECF_Msk

#define	USART_ICR_NCF_Pos (2U)

#define	USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)

#define	USART_ICR_NCF USART_ICR_NCF_Msk

#define	USART_ICR_ORECF_Pos (3U)

#define	USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

#define	USART_ICR_ORECF USART_ICR_ORECF_Msk

#define	USART_ICR_IDLECF_Pos (4U)

#define	USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

#define	USART_ICR_IDLECF USART_ICR_IDLECF_Msk

#define	USART_ICR_TCCF_Pos (6U)

#define	USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

#define	USART_ICR_TCCF USART_ICR_TCCF_Msk

#define	USART_ICR_LBDCF_Pos (8U)

#define	USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

#define	USART_ICR_LBDCF USART_ICR_LBDCF_Msk

#define	USART_ICR_CTSCF_Pos (9U)

#define	USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

#define	USART_ICR_CTSCF USART_ICR_CTSCF_Msk

#define	USART_ICR_RTOCF_Pos (11U)

#define	USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

#define	USART_ICR_RTOCF USART_ICR_RTOCF_Msk

#define	USART_ICR_EOBCF_Pos (12U)

#define	USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

#define	USART_ICR_EOBCF USART_ICR_EOBCF_Msk

#define	USART_ICR_CMCF_Pos (17U)

#define	USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

#define	USART_ICR_CMCF USART_ICR_CMCF_Msk

#define	USART_ICR_WUCF_Pos (20U)

#define	USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

#define	USART_ICR_WUCF USART_ICR_WUCF_Msk

#define	USART_RDR_RDR_Pos (0U)

#define	USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

#define	USART_RDR_RDR USART_RDR_RDR_Msk

#define	USART_TDR_TDR_Pos (0U)

#define	USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

#define	USART_TDR_TDR USART_TDR_TDR_Msk

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T0 WWDG_CR_T_0

#define	WWDG_CR_T1 WWDG_CR_T_1

#define	WWDG_CR_T2 WWDG_CR_T_2

#define	WWDG_CR_T3 WWDG_CR_T_3

#define	WWDG_CR_T4 WWDG_CR_T_4

#define	WWDG_CR_T5 WWDG_CR_T_5

#define	WWDG_CR_T6 WWDG_CR_T_6

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W0 WWDG_CFR_W_0

#define	WWDG_CFR_W1 WWDG_CFR_W_1

#define	WWDG_CFR_W2 WWDG_CFR_W_2

#define	WWDG_CFR_W3 WWDG_CFR_W_3

#define	WWDG_CFR_W4 WWDG_CFR_W_4

#define	WWDG_CFR_W5 WWDG_CFR_W_5

#define	WWDG_CFR_W6 WWDG_CFR_W_6

#define	WWDG_CFR_WDGTB_Pos (7U)

#define	WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0

#define	WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

#define	IS_ADC_ALL_INSTANCE(INSTANCE)

#define	IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))

#define	IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

#define	IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)

#define	IS_COMP_ALL_INSTANCE(INSTANCE)

#define	IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (0U)

#define	IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0U)

#define	IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0U)

#define	IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

#define	IS_DAC_ALL_INSTANCE(INSTANCE)

#define	IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

#define	IS_DMA_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_AF_INSTANCE(INSTANCE)

#define	IS_GPIO_LOCK_INSTANCE(INSTANCE)

#define	IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

#define	IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)

#define	IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

#define	IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)

#define	IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)

#define	IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)

#define	IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)

#define	IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)

#define	IS_TIM_INSTANCE(INSTANCE)

#define	IS_TIM_CC1_INSTANCE(INSTANCE)

#define	IS_TIM_CC2_INSTANCE(INSTANCE)

#define	IS_TIM_CC3_INSTANCE(INSTANCE)

#define	IS_TIM_CC4_INSTANCE(INSTANCE)

#define	IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)

#define	IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)

#define	IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)

#define	IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TIM_ETR_INSTANCE(INSTANCE)

#define	IS_TIM_XOR_INSTANCE(INSTANCE)

#define	IS_TIM_MASTER_INSTANCE(INSTANCE)

#define	IS_TIM_SLAVE_INSTANCE(INSTANCE)

#define	IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)

#define	IS_TIM_DMABURST_INSTANCE(INSTANCE)

#define	IS_TIM_BREAK_INSTANCE(INSTANCE)

#define	IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)

#define	IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)

#define	IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TIM_DMA_INSTANCE(INSTANCE)

#define	IS_TIM_DMA_CC_INSTANCE(INSTANCE)

#define	IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)

#define	IS_TIM_REMAP_INSTANCE(INSTANCE)

#define	IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))

#define	IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)

#define	IS_USART_INSTANCE(INSTANCE)

#define	IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_UART_INSTANCE(INSTANCE)

#define	IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)

#define	IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_UART_HWFLOW_INSTANCE(INSTANCE)

#define	IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)

#define	IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)

#define	IS_UART_DMA_INSTANCE(INSTANCE) (1)

#define	IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

#define	ADC1_IRQn ADC1_2_IRQn

#define	USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn

#define	USB_HP_CAN_TX_IRQn CAN_TX_IRQn

#define	COMP_IRQn COMP2_IRQn

#define	COMP1_2_IRQn COMP2_IRQn

#define	COMP1_2_3_IRQn COMP2_IRQn

#define	COMP4_5_6_IRQn COMP4_6_IRQn

#define	I2C3_ER_IRQn HRTIM1_FLT_IRQn

#define	I2C3_EV_IRQn HRTIM1_TIME_IRQn

#define	TIM15_IRQn TIM1_BRK_TIM15_IRQn

#define	TIM18_DAC2_IRQn TIM1_CC_IRQn

#define	TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn

#define	TIM16_IRQn TIM1_UP_TIM16_IRQn

#define	TIM6_DAC_IRQn TIM6_DAC1_IRQn

#define	TIM7_IRQn TIM7_DAC2_IRQn

#define	ADC1_IRQHandler ADC1_2_IRQHandler

#define	USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler

#define	USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler

#define	COMP_IRQHandler COMP2_IRQHandler

#define	COMP1_2_IRQHandler COMP2_IRQHandler

#define	COMP1_2_3_IRQHandler COMP2_IRQHandler

#define	COMP4_5_6_IRQHandler COMP4_6_IRQHandler

#define	I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler

#define	I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler

#define	TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler

#define	TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler

#define	TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler

#define	TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler

#define	TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler

#define	TIM7_IRQHandler TIM7_DAC2_IRQHandler

Enumerations
enum	IRQn_Type { NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMP_STAMP_IRQn = 2 , RTC_WKUP_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_TSC_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , CAN_TX_IRQn = 19 , CAN_RX0_IRQn = 20 , CAN_RX1_IRQn = 21 , CAN_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_TIM15_IRQn = 24 , TIM1_UP_TIM16_IRQn = 25 , TIM1_TRG_COM_TIM17_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , SPI1_IRQn = 35 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , TIM6_DAC1_IRQn = 54 , TIM7_DAC2_IRQn = 55 , COMP2_IRQn = 64 , COMP4_6_IRQn = 65 , HRTIM1_Master_IRQn = 67 , HRTIM1_TIMA_IRQn = 68 , HRTIM1_TIMB_IRQn = 69 , HRTIM1_TIMC_IRQn = 70 , HRTIM1_TIMD_IRQn = 71 , HRTIM1_TIME_IRQn = 72 , HRTIM1_FLT_IRQn = 73 , FPU_IRQn = 81 }
	STM32F334x8 devices Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.

Author

MCD Application Team

     This file contains:
      - Data structures and the address mapping for all peripherals
      - Peripheral's registers declarations and bits definition
      - Macros to access peripheral's registers hardware

Attention

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Classes

Macros

Enumerations

Detailed Description

© Copyright (c) 2016 STMicroelectronics. All rights reserved.